diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c index e2e4814..70dcae0 100644 --- a/gcc/common/config/i386/i386-common.c +++ b/gcc/common/config/i386/i386-common.c @@ -56,6 +56,7 @@ along with GCC; see the file COPYING3. If not see (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET) #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW +#define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same as -msse4.2. */ @@ -125,6 +126,7 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA_AVX2_UNSET OPTION_MASK_ISA_AVX2 #define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM #define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW +#define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same as -mno-sse4.1. */ @@ -570,6 +572,19 @@ ix86_handle_option (struct gcc_options *opts, } return true; + case OPT_mrdseed: + if (value) + { + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDSEED_SET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_SET; + } + else + { + opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDSEED_UNSET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_UNSET; + } + return true; + case OPT_mprfchw: if (value) { diff --git a/gcc/config.gcc b/gcc/config.gcc index 1a28f37..dad4c3a 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -361,7 +361,7 @@ i[34567]86-*-*) ia32intrin.h cross-stdarg.h lwpintrin.h popcntintrin.h lzcntintrin.h bmiintrin.h bmi2intrin.h tbmintrin.h avx2intrin.h fmaintrin.h f16cintrin.h rtmintrin.h - xtestintrin.h prfchwintrin.h" + xtestintrin.h rdseedintrin.h prfchwintrin.h" ;; x86_64-*-*) cpu_type=i386 @@ -375,7 +375,7 @@ x86_64-*-*) ia32intrin.h cross-stdarg.h lwpintrin.h popcntintrin.h lzcntintrin.h bmiintrin.h tbmintrin.h bmi2intrin.h avx2intrin.h fmaintrin.h f16cintrin.h rtmintrin.h - xtestintrin.h prfchwintrin.h" + xtestintrin.h rdseedintrin.h prfchwintrin.h" need_64bit_hwint=yes ;; ia64-*-*) diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c index 1529810..4616108 100644 --- a/gcc/config/i386/driver-i386.c +++ b/gcc/config/i386/driver-i386.c @@ -399,7 +399,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) unsigned int has_bmi = 0, has_bmi2 = 0, has_tbm = 0, has_lzcnt = 0; unsigned int has_hle = 0, has_rtm = 0; unsigned int has_rdrnd = 0, has_f16c = 0, has_fsgsbase = 0; - unsigned int has_prfchw = 0; + unsigned int has_rdseed = 0, has_prfchw = 0; bool arch; @@ -466,6 +466,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) has_avx2 = ebx & bit_AVX2; has_bmi2 = ebx & bit_BMI2; has_fsgsbase = ebx & bit_FSGSBASE; + has_rdseed = ebx & bit_RDSEED; has_prfchw = ecx & bit_PRFCHW; } @@ -747,12 +748,13 @@ const char *host_detect_local_cpu (int argc, const char **argv) const char *rdrnd = has_rdrnd ? " -mrdrnd" : " -mno-rdrnd"; const char *f16c = has_f16c ? " -mf16c" : " -mno-f16c"; const char *fsgsbase = has_fsgsbase ? " -mfsgsbase" : " -mno-fsgsbase"; + const char *rdseed = has_rdseed ? " -mrdseed" : " -mno-rdseed"; const char *prfchw = has_prfchw ? " -mprfchw" : " -mno-prfchw"; options = concat (options, cx16, sahf, movbe, ase, pclmul, popcnt, abm, lwp, fma, fma4, xop, bmi, bmi2, tbm, avx, avx2, sse4_2, sse4_1, lzcnt, rtm, - hle, rdrnd, f16c, fsgsbase, prfchw, NULL); + hle, rdrnd, f16c, fsgsbase, rdseed, prfchw, NULL); } done: diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c index c803c50..a4c947a 100644 --- a/gcc/config/i386/i386-c.c +++ b/gcc/config/i386/i386-c.c @@ -296,6 +296,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__RDRND__"); if (isa_flag & OPTION_MASK_ISA_F16C) def_or_undef (parse_in, "__F16C__"); + if (isa_flag & OPTION_MASK_ISA_RDSEED) + def_or_undef (parse_in, "__RDSEED__"); if (isa_flag & OPTION_MASK_ISA_PRFCHW) def_or_undef (parse_in, "__PRFCHW__"); if ((fpmath & FPMATH_SSE) && (isa_flag & OPTION_MASK_ISA_SSE)) diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index a733aa8..f7a927e 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -2767,6 +2767,7 @@ ix86_target_string (HOST_WIDE_INT isa, int flags, const char *arch, { "-mbmi2", OPTION_MASK_ISA_BMI2 }, { "-mlzcnt", OPTION_MASK_ISA_LZCNT }, { "-mhle", OPTION_MASK_ISA_HLE }, + { "-mrdseed", OPTION_MASK_ISA_RDSEED }, { "-mprfchw", OPTION_MASK_ISA_PRFCHW }, { "-mtbm", OPTION_MASK_ISA_TBM }, { "-mpopcnt", OPTION_MASK_ISA_POPCNT }, @@ -3045,6 +3046,7 @@ ix86_option_override_internal (bool main_args_p) #define PTA_RTM (HOST_WIDE_INT_1 << 32) #define PTA_HLE (HOST_WIDE_INT_1 << 33) #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34) +#define PTA_RDSEED (HOST_WIDE_INT_1 << 35) /* if this reaches 64, need to widen struct pta flags below */ static struct pta @@ -3533,6 +3535,9 @@ ix86_option_override_internal (bool main_args_p) if (processor_alias_table[i].flags & PTA_PRFCHW && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_PRFCHW)) ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW; + if (processor_alias_table[i].flags & PTA_RDSEED + && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_RDSEED)) + ix86_isa_flags |= OPTION_MASK_ISA_RDSEED; if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)) x86_prefetch_sse = true; @@ -4355,6 +4360,7 @@ ix86_valid_target_attribute_inner_p (tree args, char *p_strings[], IX86_ATTR_ISA ("rtm", OPT_mrtm), IX86_ATTR_ISA ("hle", OPT_mhle), IX86_ATTR_ISA ("prfchw", OPT_mprfchw), + IX86_ATTR_ISA ("rdseed", OPT_mrdseed), /* enum options */ IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_), @@ -26110,6 +26116,11 @@ enum ix86_builtins IX86_BUILTIN_RDRAND32_STEP, IX86_BUILTIN_RDRAND64_STEP, + /* RDSEED instructions. */ + IX86_BUILTIN_RDSEED16_STEP, + IX86_BUILTIN_RDSEED32_STEP, + IX86_BUILTIN_RDSEED64_STEP, + /* F16C instructions. */ IX86_BUILTIN_CVTPH2PS, IX86_BUILTIN_CVTPH2PS256, @@ -27931,6 +27942,15 @@ ix86_init_mmx_sse_builtins (void) def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi", V16QI_FTYPE_V16QI_QI_INT, IX86_BUILTIN_VEC_SET_V16QI); + /* RDSEED */ + def_builtin (OPTION_MASK_ISA_RDSEED, "__builtin_ia32_rdseed_hi_step", + INT_FTYPE_PUSHORT, IX86_BUILTIN_RDSEED16_STEP); + def_builtin (OPTION_MASK_ISA_RDSEED, "__builtin_ia32_rdseed_si_step", + INT_FTYPE_PUNSIGNED, IX86_BUILTIN_RDSEED32_STEP); + def_builtin (OPTION_MASK_ISA_RDSEED && OPTION_MASK_ISA_64BIT, + "__builtin_ia32_rdseed_di_step", + INT_FTYPE_PULONGLONG, IX86_BUILTIN_RDSEED64_STEP); + /* Add FMA4 multi-arg argument instructions */ for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++) { @@ -30255,6 +30275,46 @@ rdrand_step: gen_rtx_IF_THEN_ELSE (SImode, pat, op2, op1))); return target; + case IX86_BUILTIN_RDSEED16_STEP: + icode = CODE_FOR_rdseedhi_1; + mode0 = HImode; + goto rdseed_step; + + case IX86_BUILTIN_RDSEED32_STEP: + icode = CODE_FOR_rdseedsi_1; + mode0 = SImode; + goto rdseed_step; + + case IX86_BUILTIN_RDSEED64_STEP: + icode = CODE_FOR_rdseeddi_1; + mode0 = DImode; + +rdseed_step: + op0 = gen_reg_rtx (mode0); + emit_insn (GEN_FCN (icode) (op0)); + + arg0 = CALL_EXPR_ARG (exp, 0); + op1 = expand_normal (arg0); + if (!address_operand (op1, VOIDmode)) + { + op1 = convert_memory_address (Pmode, op1); + op1 = copy_addr_to_reg (op1); + } + emit_move_insn (gen_rtx_MEM (mode0, op1), op0); + + op2 = gen_reg_rtx (QImode); + + pat = gen_rtx_LTU (QImode, gen_rtx_REG (CCCmode, FLAGS_REG), + const0_rtx); + emit_insn (gen_rtx_SET (VOIDmode, op2, pat)); + + if (target == 0) + target = gen_reg_rtx (SImode); + + emit_insn (gen_zero_extendqisi2 (target, op2)); + + return target; + case IX86_BUILTIN_GATHERSIV2DF: icode = CODE_FOR_avx2_gathersiv2df; goto gather_gen; diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 8f87f12..a6ce0ce 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -76,6 +76,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #define TARGET_F16C OPTION_ISA_F16C #define TARGET_RTM OPTION_ISA_RTM #define TARGET_HLE OPTION_ISA_HLE +#define TARGET_RDSEED OPTION_ISA_RDSEED #define TARGET_PRFCHW OPTION_ISA_PRFCHW #define TARGET_LP64 OPTION_ABI_64 diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index f8a6c3a..afe33fa 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -206,6 +206,9 @@ ;; For RDRAND support UNSPECV_RDRAND + ;; For RDSEED support + UNSPECV_RDSEED + ;; For RTM support UNSPECV_XBEGIN UNSPECV_XEND @@ -6701,6 +6704,18 @@ (match_operand:MODEF 2 "nonimmediate_operand")))] "(TARGET_80387 && X87_ENABLE_ARITH (mode)) || (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)") + +(define_insn "rdseed_1" + [(set (match_operand:SWI248 0 "register_operand" "=r") + (unspec_volatile:SWI248 [(const_int 0)] UNSPECV_RDSEED)) + (set (reg:CCC FLAGS_REG) + (unspec_volatile:CCC [(const_int 0)] UNSPECV_RDSEED))] + "TARGET_RDSEED" + "rdseed\t%0" + [(set_attr "type" "other") + (set_attr "prefix_extra" "1")]) + + ;; Multiply instructions diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index 223a646..ccada37 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -532,6 +532,10 @@ mhle Target Report Mask(ISA_HLE) Var(ix86_isa_flags) Save Support Hardware Lock Elision prefixes +mrdseed +Target Report Mask(ISA_RDSEED) Var(ix86_isa_flags) Save +Support RDSEED instruction + mprfchw Target Report Mask(ISA_PRFCHW) Var(ix86_isa_flags) Save Support PREFETCHW instruction diff --git a/gcc/config/i386/rdseedintrin.h b/gcc/config/i386/rdseedintrin.h new file mode 100644 index 0000000..afd6ce8 --- /dev/null +++ b/gcc/config/i386/rdseedintrin.h @@ -0,0 +1,58 @@ +/* Copyright (C) 2012 Free Software Foundation, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +#if !defined _X86INTRIN_H_INCLUDED +# error "Never use directly; include instead." +#endif + +#ifndef __RDSEED__ +# error "RDSEED instruction not enabled" +#endif /* __RDSEED__ */ + +#ifndef _RDSEEDINTRIN_H_INCLUDED +#define _RDSEEDINTRIN_H_INCLUDED + +extern __inline int +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_rdseed16_step (unsigned short *p) +{ + return __builtin_ia32_rdseed_hi_step (p); +} + +extern __inline int +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_rdseed32_step (unsigned int *p) +{ + return __builtin_ia32_rdseed_si_step (p); +} + +#ifdef __x86_64__ +extern __inline int +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_rdseed64_step (unsigned long long *p) +{ + return __builtin_ia32_rdseed_di_step (p); +} +#endif + +#endif /* _RDSEEDINTRIN_H_INCLUDED */ diff --git a/gcc/config/i386/x86intrin.h b/gcc/config/i386/x86intrin.h index 70b2316..9dee9ef 100644 --- a/gcc/config/i386/x86intrin.h +++ b/gcc/config/i386/x86intrin.h @@ -97,6 +97,10 @@ #include #endif +#ifdef __RDSEED__ +#include +#endif + #ifdef __PRFCHW__ #include #endif diff --git a/gcc/testsuite/g++.dg/other/i386-2.C b/gcc/testsuite/g++.dg/other/i386-2.C index c40f3d3..47fda70 100644 --- a/gcc/testsuite/g++.dg/other/i386-2.C +++ b/gcc/testsuite/g++.dg/other/i386-2.C @@ -1,5 +1,5 @@ /* { dg-do compile { target i?86-*-* x86_64-*-* } } */ -/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mprfchw" } */ +/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw" } */ /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h, xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h, diff --git a/gcc/testsuite/g++.dg/other/i386-3.C b/gcc/testsuite/g++.dg/other/i386-3.C index 03bdfd2..ad477fa 100644 --- a/gcc/testsuite/g++.dg/other/i386-3.C +++ b/gcc/testsuite/g++.dg/other/i386-3.C @@ -1,5 +1,5 @@ /* { dg-do compile { target i?86-*-* x86_64-*-* } } */ -/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mprfchw" } */ +/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw" } */ /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h, xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h, diff --git a/gcc/testsuite/gcc.target/i386/rdseed16-1.c b/gcc/testsuite/gcc.target/i386/rdseed16-1.c new file mode 100644 index 0000000..fe637f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/rdseed16-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mrdseed -O2" } */ +/* { dg-final { scan-assembler "rdseed\[ \\t\]+" } } */ + +#include + +void extern +rdseed_test (unsigned short *p) +{ + volatile int r; + r = _rdseed16_step (p); +} + diff --git a/gcc/testsuite/gcc.target/i386/rdseed32-1.c b/gcc/testsuite/gcc.target/i386/rdseed32-1.c new file mode 100644 index 0000000..646dff2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/rdseed32-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mrdseed -O2" } */ +/* { dg-final { scan-assembler "rdseed\[ \\t\]+" } } */ + +#include + +void extern +rdseed_test (unsigned int *p) +{ + volatile int r; + r = _rdseed32_step (p); +} + diff --git a/gcc/testsuite/gcc.target/i386/rdseed64-1.c b/gcc/testsuite/gcc.target/i386/rdseed64-1.c new file mode 100644 index 0000000..bdacd7a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/rdseed64-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mrdseed -O2" } */ +/* { dg-final { scan-assembler "rdseed\[ \\t\]+" } } */ + +#include + +void extern +rdseed_test (unsigned long long *p) +{ + volatile int r; + r = _rdseed64_step (p); +} + diff --git a/gcc/testsuite/gcc.target/i386/sse-12.c b/gcc/testsuite/gcc.target/i386/sse-12.c index 19e0071..cb3ab18 100644 --- a/gcc/testsuite/gcc.target/i386/sse-12.c +++ b/gcc/testsuite/gcc.target/i386/sse-12.c @@ -3,7 +3,7 @@ popcntintrin.h and mm_malloc.h are usable with -O -std=c89 -pedantic-errors. */ /* { dg-do compile } */ -/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mprfchw" } */ +/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw" } */ #include diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c index 7a2bdb3..fe2bf46 100644 --- a/gcc/testsuite/gcc.target/i386/sse-13.c +++ b/gcc/testsuite/gcc.target/i386/sse-13.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mprfchw" } */ +/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw" } */ #include diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c index 8b19a88..8877e31 100644 --- a/gcc/testsuite/gcc.target/i386/sse-14.c +++ b/gcc/testsuite/gcc.target/i386/sse-14.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mprfchw" } */ +/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw" } */ #include diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.target/i386/sse-22.c index 99dddfd..ec5ccb8 100644 --- a/gcc/testsuite/gcc.target/i386/sse-22.c +++ b/gcc/testsuite/gcc.target/i386/sse-22.c @@ -50,7 +50,7 @@ #ifndef DIFFERENT_PRAGMAS -#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,prfchw") +#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw") #endif /* Following intrinsics require immediate arguments. They @@ -264,7 +264,7 @@ test_2 (_mm_clmulepi64_si128, __m128i, __m128i, __m128i, 1) /* x86intrin.h (FMA4/XOP/LWP/BMI/BMI2/TBM/LZCNT/FMA). */ #ifdef DIFFERENT_PRAGMAS -#pragma GCC target ("fma4,xop,lwp,bmi,bmi2,tbm,lzcnt,fma,prfchw") +#pragma GCC target ("fma4,xop,lwp,bmi,bmi2,tbm,lzcnt,fma,rdseed,prfchw") #endif #include /* xopintrin.h */ diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c index a06ee5e..3b26d99 100644 --- a/gcc/testsuite/gcc.target/i386/sse-23.c +++ b/gcc/testsuite/gcc.target/i386/sse-23.c @@ -183,7 +183,7 @@ /* rtmintrin.h */ #define __builtin_ia32_xabort(M) __builtin_ia32_xabort(1) -#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,prfchw") +#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw") #include #include #include