On Wed, 2025-03-05 at 10:52 +0800, Lulu Cheng wrote: > LGTM! Pushed to trunk. The draft of gcc-14 backport is attached, I'll push it if it builds & tests fine and there's no objection.
-- Xi Ruoyao <xry...@xry111.site> School of Aerospace Science and Technology, Xidian University
From 6e4ca8b9c4944ffe896f4d8952f29c4cd518df22 Mon Sep 17 00:00:00 2001 From: Xi Ruoyao <xry...@xry111.site> Date: Sun, 2 Mar 2025 19:02:50 +0800 Subject: [gcc14 PATCH] LoongArch: Fix incorrect reorder of __lsx_vldx and __lasx_xvldx [PR119084] They could be incorrectly reordered with store instructions like st.b because the RTL expression does not have a memory_operand or a (mem) expression. The incorrect reorder has been observed in openh264 LTO build. Expand them to a (mem) expression instead of unspec to fix the issue. Closes: https://github.com/cisco/openh264/issues/3857 (cherry picked from commit 4856292f7a680ec478e7607f1b71781996d7d542) Edited to remove the loongarch.cc change which is not needed for gcc-14 branch. gcc/ChangeLog: PR target/119084 * config/loongarch/lasx.md (UNSPEC_LASX_XVLDX): Remove. (lasx_xvldx): Remove. * config/loongarch/lsx.md (UNSPEC_LSX_VLDX): Remove. (lsx_vldx): Remove. * config/loongarch/simd.md (QIVEC): New define_mode_iterator. (<simd_isa>_<x>vldx): New define_expand. gcc/testsuite/ChangeLog: PR target/119084 * gcc.target/loongarch/pr119084.c: New test. --- gcc/config/loongarch/lasx.md | 13 ---------- gcc/config/loongarch/lsx.md | 13 ---------- gcc/config/loongarch/simd.md | 10 ++++++++ gcc/testsuite/gcc.target/loongarch/pr119084.c | 24 +++++++++++++++++++ 4 files changed, 34 insertions(+), 26 deletions(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/pr119084.c diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md index 94bbd0c26bb..fe32194e811 100644 --- a/gcc/config/loongarch/lasx.md +++ b/gcc/config/loongarch/lasx.md @@ -155,7 +155,6 @@ (define_c_enum "unspec" [ UNSPEC_LASX_XVSSRLRN UNSPEC_LASX_XVEXTL_QU_DU UNSPEC_LASX_XVLDI - UNSPEC_LASX_XVLDX UNSPEC_LASX_XVSTX UNSPEC_LASX_VECINIT_MERGE UNSPEC_LASX_VEC_SET_INTERNAL @@ -4679,18 +4678,6 @@ (define_insn "lasx_xvldi" [(set_attr "type" "simd_load") (set_attr "mode" "V4DI")]) -(define_insn "lasx_xvldx" - [(set (match_operand:V32QI 0 "register_operand" "=f") - (unspec:V32QI [(match_operand:DI 1 "register_operand" "r") - (match_operand:DI 2 "reg_or_0_operand" "rJ")] - UNSPEC_LASX_XVLDX))] - "ISA_HAS_LASX" -{ - return "xvldx\t%u0,%1,%z2"; -} - [(set_attr "type" "simd_load") - (set_attr "mode" "V32QI")]) - (define_insn "lasx_xvstx" [(set (mem:V32QI (plus:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "reg_or_0_operand" "rJ"))) diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md index 5ee5845e84b..67ba8e8ad5d 100644 --- a/gcc/config/loongarch/lsx.md +++ b/gcc/config/loongarch/lsx.md @@ -100,7 +100,6 @@ (define_c_enum "unspec" [ UNSPEC_LSX_VSSRLRN UNSPEC_LSX_VLDI UNSPEC_LSX_VSHUF_B - UNSPEC_LSX_VLDX UNSPEC_LSX_VSTX UNSPEC_LSX_VEXTL_QU_DU UNSPEC_LSX_VSETEQZ_V @@ -3070,18 +3069,6 @@ (define_insn "lsx_vshuf_b" [(set_attr "type" "simd_shf") (set_attr "mode" "V16QI")]) -(define_insn "lsx_vldx" - [(set (match_operand:V16QI 0 "register_operand" "=f") - (unspec:V16QI [(match_operand:DI 1 "register_operand" "r") - (match_operand:DI 2 "reg_or_0_operand" "rJ")] - UNSPEC_LSX_VLDX))] - "ISA_HAS_LSX" -{ - return "vldx\t%w0,%1,%z2"; -} - [(set_attr "type" "simd_load") - (set_attr "mode" "V16QI")]) - (define_insn "lsx_vstx" [(set (mem:V16QI (plus:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "reg_or_0_operand" "rJ"))) diff --git a/gcc/config/loongarch/simd.md b/gcc/config/loongarch/simd.md index 00ff2823a4e..691e7195636 100644 --- a/gcc/config/loongarch/simd.md +++ b/gcc/config/loongarch/simd.md @@ -113,6 +113,16 @@ (define_mode_attr bitimm [(V16QI "uimm3") (V32QI "uimm3") ;; instruction here so we can avoid duplicating logics. ;; ======================================================================= +;; REG + REG load + +(define_mode_iterator QIVEC [(V16QI "ISA_HAS_LSX") (V32QI "ISA_HAS_LASX")]) +(define_expand "<simd_isa>_<x>vldx" + [(set (match_operand:QIVEC 0 "register_operand" "=f") + (mem:QIVEC (plus:DI (match_operand:DI 1 "register_operand") + (match_operand:DI 2 "register_operand"))))] + "TARGET_64BIT") + + ;; ;; FP vector rounding instructions ;; diff --git a/gcc/testsuite/gcc.target/loongarch/pr119084.c b/gcc/testsuite/gcc.target/loongarch/pr119084.c new file mode 100644 index 00000000000..b5943303851 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/pr119084.c @@ -0,0 +1,24 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mlsx" } */ +/* { dg-require-effective-target loongarch_sx_hw } */ + +typedef signed char V16QI __attribute__ ((vector_size (16))); +static char x[128]; + +__attribute__ ((noipa)) int +noopt (int x) +{ + return x; +} + +int +main (void) +{ + int t = noopt (32); + + x[32] = 1; + + V16QI y = __builtin_lsx_vldx (x, t); + if (y[0] != 1) + __builtin_trap (); +} -- 2.48.1
