On 2/24/25 6:10 PM, Edwin Lu wrote:
So I preferred the earlier approach of disabling speculation of the
vsetvls, though I'm guessing you're looking at this approach because
that was insufficient?
I don't think that it was because it was insufficient, but that it might
be too constraining. I'm not exactly certain if there is the possibility
where speculatively issuing some vsetvls in some situations could
improve perf.
On an out of order core I would expect the hardware to do the
speculation and doing it in the compiler is of marginal value, if any.
I think with this patch, it targets the specific issue
we're facing directly which is updating vl=0 when it's unnecessary. I
don't know which patch would be better so I'm putting this out there as
a potential alternative.
I suspect (but haven't verified) that the only time you'll see the
conditional branch and the vsetvl in the ready queue together is in the
speculative case. Now it may be the case that you can be more targeted
in inhibiting speculation, but again, for an out of order core I don't
think it's actually going to matter.
Essentially when we aren't speculating the conditional branch will be
dependent on all the instructions in the block. So the conditional
branch won't go into the ready queue until after everything else has issued.
Given we're not planning to move forward until stage1 reopens, you've
got time to play with it internally. I've also got a mental todo to
check with our designers to see if we have any sensitivity to this issue.
jeff
