[PATCH] RISC-V: unrecognizable insn ICE in xtheadvector/pr114194.c on 32bit targets

[Jin Ma]

        PR target/118601

gcc/ChangeLog:

        * config/riscv/riscv.cc (riscv_use_by_pieces_infrastructure_p):
        Exclude XTheadVector.

Reported-by: Edwin Lu <e...@rivosinc.com>
---
 gcc/config/riscv/riscv.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 819e1538741..e5776aa0fbe 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -13826,7 +13826,7 @@ riscv_use_by_pieces_infrastructure_p (unsigned 
HOST_WIDE_INT size,
   /* For set/clear with size > UNITS_PER_WORD, by pieces uses vector broadcasts
      with UNITS_PER_WORD size pieces.  Use setmem<mode> instead which can use
      bigger chunks.  */
-  if (TARGET_VECTOR && stringop_strategy & STRATEGY_VECTOR
+  if (TARGET_VECTOR && !TARGET_XTHEADVECTOR && stringop_strategy & 
STRATEGY_VECTOR
       && (op == CLEAR_BY_PIECES || op == SET_BY_PIECES)
       && speed_p && size > UNITS_PER_WORD)
     return false;
-- 
2.25.1