We have some vector instructions for operations on 128-bit integer, i.e.
TImode, vectors. Previously they had been modeled with unspecs, but
it's more natural to just model them with TImode vector RTL expressions.
For the preparation, allow moving V1TImode and V2TImode vectors in LSX
and LASX registers so we won't get a reload failure when we start to
save TImode vectors in these registers.
This implicitly depends on the vrepli optimization: without it we'd try
"vrepli.q" which does not really exist and trigger an ICE.
gcc/ChangeLog:
* config/loongarch/lsx.md (mov<LSX:mode>): Remove.
(movmisalign<LSX:mode>): Remove.
(mov<LSX:mode>_lsx): Remove.
* config/loongarch/lasx.md (mov<LASX:mode>): Remove.
(movmisalign<LASX:mode>): Remove.
(mov<LASX:mode>_lasx): Remove.
* config/loongarch/simd.md (ALLVEC_TI): New mode iterator.
(mov<ALLVEC_TI:mode): New define_expand.
(movmisalign<ALLVEC_TI:mode>): Likewise.
(mov<ALLVEC_TI:mode>_simd): New define_insn_and_split.
---
gcc/config/loongarch/lasx.md | 40 ----------------------------------
gcc/config/loongarch/lsx.md | 36 -------------------------------
gcc/config/loongarch/simd.md | 42 ++++++++++++++++++++++++++++++++++++
3 files changed, 42 insertions(+), 76 deletions(-)
diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
index a37c85a25a4..d82ad61be60 100644
--- a/gcc/config/loongarch/lasx.md
+++ b/gcc/config/loongarch/lasx.md
@@ -699,46 +699,6 @@ (define_expand "lasx_xvrepli<mode>"
DONE;
})
-(define_expand "mov<mode>"
- [(set (match_operand:LASX 0)
- (match_operand:LASX 1))]
- "ISA_HAS_LASX"
-{
- if (loongarch_legitimize_move (<MODE>mode, operands[0], operands[1]))
- DONE;
-})
-
-
-(define_expand "movmisalign<mode>"
- [(set (match_operand:LASX 0)
- (match_operand:LASX 1))]
- "ISA_HAS_LASX"
-{
- if (loongarch_legitimize_move (<MODE>mode, operands[0], operands[1]))
- DONE;
-})
-
-;; 256-bit LASX modes can only exist in LASX registers or memory.
-(define_insn "mov<mode>_lasx"
- [(set (match_operand:LASX 0 "nonimmediate_operand" "=f,f,R,*r,*f")
- (match_operand:LASX 1 "move_operand" "fYGYI,R,f,*f,*r"))]
- "ISA_HAS_LASX"
- { return loongarch_output_move (operands); }
- [(set_attr "type" "simd_move,simd_load,simd_store,simd_copy,simd_insert")
- (set_attr "mode" "<MODE>")
- (set_attr "length" "8,4,4,4,4")])
-
-
-(define_split
- [(set (match_operand:LASX 0 "nonimmediate_operand")
- (match_operand:LASX 1 "move_operand"))]
- "reload_completed && ISA_HAS_LASX
- && loongarch_split_move_p (operands[0], operands[1])"
- [(const_int 0)]
-{
- loongarch_split_move (operands[0], operands[1]);
- DONE;
-})
;; LASX
(define_insn "add<mode>3"
diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md
index ca0066a21ed..bcc5ae85fb3 100644
--- a/gcc/config/loongarch/lsx.md
+++ b/gcc/config/loongarch/lsx.md
@@ -575,42 +575,6 @@ (define_insn "lsx_vshuf_<lsxfmt_f>"
[(set_attr "type" "simd_sld")
(set_attr "mode" "<MODE>")])
-(define_expand "mov<mode>"
- [(set (match_operand:LSX 0)
- (match_operand:LSX 1))]
- "ISA_HAS_LSX"
-{
- if (loongarch_legitimize_move (<MODE>mode, operands[0], operands[1]))
- DONE;
-})
-
-(define_expand "movmisalign<mode>"
- [(set (match_operand:LSX 0)
- (match_operand:LSX 1))]
- "ISA_HAS_LSX"
-{
- if (loongarch_legitimize_move (<MODE>mode, operands[0], operands[1]))
- DONE;
-})
-
-(define_insn "mov<mode>_lsx"
- [(set (match_operand:LSX 0 "nonimmediate_operand" "=f,f,R,*r,*f,*r")
- (match_operand:LSX 1 "move_operand" "fYGYI,R,f,*f,*r,*r"))]
- "ISA_HAS_LSX"
-{ return loongarch_output_move (operands); }
- [(set_attr "type"
"simd_move,simd_load,simd_store,simd_copy,simd_insert,simd_copy")
- (set_attr "mode" "<MODE>")])
-
-(define_split
- [(set (match_operand:LSX 0 "nonimmediate_operand")
- (match_operand:LSX 1 "move_operand"))]
- "reload_completed && ISA_HAS_LSX
- && loongarch_split_move_p (operands[0], operands[1])"
- [(const_int 0)]
-{
- loongarch_split_move (operands[0], operands[1]);
- DONE;
-})
;; Integer operations
(define_insn "add<mode>3"
diff --git a/gcc/config/loongarch/simd.md b/gcc/config/loongarch/simd.md
index 7605b17d21e..61fc1ab20ad 100644
--- a/gcc/config/loongarch/simd.md
+++ b/gcc/config/loongarch/simd.md
@@ -130,6 +130,48 @@ (define_mode_attr bitimm [(V16QI "uimm3") (V32QI "uimm3")
;; instruction here so we can avoid duplicating logics.
;; =======================================================================
+
+;; Move
+
+;; Some immediate values in V1TI or V2TI may be stored in LSX or LASX
+;; registers, thus we need to allow moving them for reload.
+(define_mode_iterator ALLVEC_TI [ALLVEC
+ (V1TI "ISA_HAS_LSX")
+ (V2TI "ISA_HAS_LASX")])
+
+(define_expand "mov<mode>"
+ [(set (match_operand:ALLVEC_TI 0)
+ (match_operand:ALLVEC_TI 1))]
+ ""
+{
+ if (loongarch_legitimize_move (<MODE>mode, operands[0], operands[1]))
+ DONE;
+})
+
+(define_expand "movmisalign<mode>"
+ [(set (match_operand:ALLVEC_TI 0)
+ (match_operand:ALLVEC_TI 1))]
+ ""
+{
+ if (loongarch_legitimize_move (<MODE>mode, operands[0], operands[1]))
+ DONE;
+})
+
+(define_insn_and_split "mov<mode>_simd"
+ [(set (match_operand:ALLVEC_TI 0 "nonimmediate_operand" "=f,f,R,*r,*f,*r")
+ (match_operand:ALLVEC_TI 1 "move_operand" "fYGYI,R,f,*f,*r,*r"))]
+ ""
+{ return loongarch_output_move (operands); }
+ "reload_completed && loongarch_split_move_p (operands[0], operands[1])"
+ [(const_int 0)]
+{
+ loongarch_split_move (operands[0], operands[1]);
+ DONE;
+}
+ [(set_attr "type"
"simd_move,simd_load,simd_store,simd_copy,simd_insert,simd_copy")
+ (set_attr "mode" "<MODE>")])
+
+
;;
;; FP vector rounding instructions
;;
--
2.48.1
