On 1/19/25 7:32 AM, Jin Ma wrote:
gcc/ChangeLog:
* config/riscv/riscv.md: Change 'r' to 'p'.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/prefetch-zicbop-ice.c: New test.
I think that rather than adjusting the constraint we should probably
adjust the operand predicate. In general we want the predicates to
represent what the hardware can do.
Accepting "address_operand" here implies that the prefetch opcodes can
accept any valid address for their mode. That's not the case for
prefetch. In particular the low 5 bits in the offset must be zero
according to the ISA specification. This also implies that for an
absolute address that the low 5 bits of that address must be zero.
We could certainly create a new predicate that allows immediate operands
and one could construct testcases that would use it, but I don't see it
as all that useful in practice. So I'm inclined to go with the simpler
solution here and only allow register indirect addresses with a zero offset.
That's how Wang Pencheng's patch works. I still need to re-review
Tsukasa's patch from a while back. But my current inclination is to
take Wang Pencheng's patch as I think it's more correct. I'll likely
take testcases from all the patches in this space.
Jeff
