Hi all, AVX10 has been published for one and half year and we have got many feedbacks on that, one of the feedback is on whether the alias option -mavx10.x should point to 256 or 512.
If you also pay attention to LLVM community, you might see this thread related to AVX10 options just sent out several hours ago: [X86][AVX10] Disable m[no-]avx10.1 and switch m[no-]avx10.2 to alias of 512 bit options https://github.com/llvm/llvm-project/pull/124511 In GCC, we will also do so. This RFC patch is slightly different with LLVM, just including: - Switch -m[no-]avx10.2 to alias of 512 bit options. - Change -mno-avx10.[1,2]-512 to disable both 256 and 512 instructions. This will also result in -mno-avx10.2 would still disable both 256 and 512 insts according to new alias point to 512. But not including disabling -m[no-]avx10.1, since I still want more input on how to handle that. We actually have three choices on that: a. Directly re-alias -m[no-]avx10.1 to -m[no-]avx10.1-512 GCC 15 and backport to GCC 14. b. Disable -m[no]-avx10.1 in GCC 15, and add it back with -m[no-]avx10.1-512 in the future. This is for in case if someone cross compile with different versions of GCC with -mavx10.1, it might get unexpected result sliently. c. Disable -m[no]-avx10.1 in GCC 15, and never add it back. Since the option has been 256 bit, changing them back and forth is messy. It might be the final chance we could change the alias option since real AVX10.1 hardware is coming soon. And it is only x86 specific, so it might still squeeze into GCC 15 at this time. I call this patch RFC patch since we also need to change the doc and testcases accordingly, which makes this patch incomplete. Discussion and input is welcomed on this topic. Thx, Haochen --- gcc/common/config/i386/i386-common.cc | 30 +++++++++++++-------------- gcc/common/config/i386/i386-isas.h | 2 +- gcc/config/i386/i386-options.cc | 2 +- gcc/config/i386/i386.opt | 4 ++-- gcc/doc/extend.texi | 8 ++++--- gcc/doc/sourcebuild.texi | 4 ++-- 6 files changed, 25 insertions(+), 25 deletions(-) diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc index 52ad1c5acd1..3891fca8ecb 100644 --- a/gcc/common/config/i386/i386-common.cc +++ b/gcc/common/config/i386/i386-common.cc @@ -325,14 +325,12 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_APX_F_UNSET OPTION_MASK_ISA2_APX_F #define OPTION_MASK_ISA2_EVEX512_UNSET OPTION_MASK_ISA2_EVEX512 #define OPTION_MASK_ISA2_USER_MSR_UNSET OPTION_MASK_ISA2_USER_MSR -#define OPTION_MASK_ISA2_AVX10_1_256_UNSET \ - (OPTION_MASK_ISA2_AVX10_1_256 | OPTION_MASK_ISA2_AVX10_1_512_UNSET \ - | OPTION_MASK_ISA2_AVX10_2_256_UNSET) -#define OPTION_MASK_ISA2_AVX10_1_512_UNSET \ - (OPTION_MASK_ISA2_AVX10_1_512 | OPTION_MASK_ISA2_AVX10_2_512_UNSET) -#define OPTION_MASK_ISA2_AVX10_2_256_UNSET OPTION_MASK_ISA2_AVX10_2_256 -#define OPTION_MASK_ISA2_AVX10_2_512_UNSET \ - (OPTION_MASK_ISA2_AVX10_2_512 | OPTION_MASK_ISA2_AMX_AVX512_UNSET) +#define OPTION_MASK_ISA2_AVX10_1_UNSET \ + (OPTION_MASK_ISA2_AVX10_1_256 | OPTION_MASK_ISA2_AVX10_1_512 \ + | OPTION_MASK_ISA2_AVX10_2_UNSET) +#define OPTION_MASK_ISA2_AVX10_2_UNSET \ + (OPTION_MASK_ISA2_AVX10_2_256 | OPTION_MASK_ISA2_AVX10_2_512 \ + OPTION_MASK_ISA2_AMX_AVX512_UNSET) #define OPTION_MASK_ISA2_AMX_AVX512_UNSET OPTION_MASK_ISA2_AMX_AVX512 #define OPTION_MASK_ISA2_AMX_TF32_UNSET OPTION_MASK_ISA2_AMX_TF32 #define OPTION_MASK_ISA2_AMX_TRANSPOSE_UNSET OPTION_MASK_ISA2_AMX_TRANSPOSE @@ -1378,8 +1376,8 @@ ix86_handle_option (struct gcc_options *opts, } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_256_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_256_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_UNSET; opts->x_ix86_no_avx10_1_explicit = 1; } return true; @@ -1394,8 +1392,8 @@ ix86_handle_option (struct gcc_options *opts, } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_512_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_512_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_UNSET; opts->x_ix86_no_avx10_1_explicit = 1; } return true; @@ -1410,8 +1408,8 @@ ix86_handle_option (struct gcc_options *opts, } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_2_256_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_2_256_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_2_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_2_UNSET; } return true; @@ -1425,8 +1423,8 @@ ix86_handle_option (struct gcc_options *opts, } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_2_512_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_2_512_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_2_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_2_UNSET; } return true; diff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/config/i386/i386-isas.h index 8976b031807..ac3bb13e137 100644 --- a/gcc/common/config/i386/i386-isas.h +++ b/gcc/common/config/i386/i386-isas.h @@ -186,7 +186,7 @@ ISA_NAMES_TABLE_START ISA_NAMES_TABLE_ENTRY("avx10.1", FEATURE_AVX10_1_256, P_NONE, "-mavx10.1") ISA_NAMES_TABLE_ENTRY("avx10.1-256", FEATURE_AVX10_1_256, P_AVX10_1_256, "-mavx10.1-256") ISA_NAMES_TABLE_ENTRY("avx10.1-512", FEATURE_AVX10_1_512, P_AVX10_1_512, "-mavx10.1-512") - ISA_NAMES_TABLE_ENTRY("avx10.2", FEATURE_AVX10_2_256, P_NONE, "-mavx10.2") + ISA_NAMES_TABLE_ENTRY("avx10.2", FEATURE_AVX10_2_512, P_NONE, "-mavx10.2") ISA_NAMES_TABLE_ENTRY("avx10.2-256", FEATURE_AVX10_2_256, P_NONE, "-mavx10.2-256") ISA_NAMES_TABLE_ENTRY("avx10.2-512", FEATURE_AVX10_2_512, P_NONE, "-mavx10.2-512") ISA_NAMES_TABLE_ENTRY("amx-avx512", FEATURE_AMX_AVX512, P_NONE, diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc index 3467ab0bbeb..ab9b2a43f69 100644 --- a/gcc/config/i386/i386-options.cc +++ b/gcc/config/i386/i386-options.cc @@ -1137,7 +1137,7 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[], IX86_ATTR_ISA ("avx10.1", OPT_mavx10_1_256), IX86_ATTR_ISA ("avx10.1-256", OPT_mavx10_1_256), IX86_ATTR_ISA ("avx10.1-512", OPT_mavx10_1_512), - IX86_ATTR_ISA ("avx10.2", OPT_mavx10_2_256), + IX86_ATTR_ISA ("avx10.2", OPT_mavx10_2_512), IX86_ATTR_ISA ("avx10.2-256", OPT_mavx10_2_256), IX86_ATTR_ISA ("avx10.2-512", OPT_mavx10_2_512), IX86_ATTR_ISA ("amx-avx512", OPT_mamx_avx512), diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index 5c889b72cc5..3ba8fa76a27 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -1389,9 +1389,9 @@ Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX10.1-512 and AVX10.2-512 built-in functions and code generation. mavx10.2 -Target Alias(mavx10.2-256) +Target Alias(mavx10.2-512) Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, -AVX10.1 and AVX10.2 built-in functions and code generation. +AVX10.1-512 and AVX10.2-512 built-in functions and code generation. mamx-avx512 Target Mask(ISA2_AMX_AVX512) Var(ix86_isa_flags2) Save diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 2764597a479..6349b5a4874 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -7619,17 +7619,19 @@ Enable/disable the generation of the AVX10.1 512 bit instructions. @cindex @code{target("avx10.2")} function attribute, x86 @item avx10.2 @itemx no-avx10.2 -Enable/disable the generation of the AVX10.2 instructions. +Enable the generation of the AVX10.2-512 instructions. +Disable the generation of the AVX10.2 instructions. @cindex @code{target("avx10.2-256")} function attribute, x86 @item avx10.2-256 @itemx no-avx10.2-256 -Enable/disbale the generation of the AVX10.2 instructions. +Enable/disable the generation of the AVX10.2-256 instructions. @cindex @code{target("avx10.2-512")} function attribute, x86 @item avx10.2-512 @itemx no-avx10.2-512 -Enable/disable the generation of the AVX10.2 512 bit instructions. +Enable the generation of the AVX10.2-512 instructions. +Disable the generation of the AVX10.2 instructions. @cindex @code{target("amx-avx512")} function attribute, x86 @item amx-avx512 diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index 98ede70f23c..0f3ee941e07 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -2621,10 +2621,10 @@ Target supports the execution of @code{avx10.1} instructions. Target supports the execution of @code{avx10.1-512} instructions. @item avx10.2 -Target supports the execution of @code{avx10.2} instructions. +Target supports the execution of @code{avx10.2-512} instructions. @item avx10.2-256 -Target supports the execution of @code{avx10.2} instructions. +Target supports the execution of @code{avx10.2-256} instructions. @item avx10.2-512 Target supports the execution of @code{avx10.2-512} instructions. -- 2.31.1
