The RISC-V backend has checks to verify that every used insn has an
associated type and that every insn type maps to some reservation in the
DFA model. If either test fails we ICE.
With the cpu/isa allowed to vary independently from the tune/scheduler
model, it's entirely possible (in fact trivial) to trigger those kinds
of ICEs.
This patch "fixes" the ICEs for xiangshan-nanhu by throwing every
unknown insn type into a special bucket I wouldn't be surprised if a
few of them are implemented (like rotates as the chip seems to have
other bitmanip extensions). But I know nothing about this design and
the DFA author hasn't responded to requests to update the DFA in ~6 months.
This should dramatically reduce the number of ICEs in the testsuite if
someone were to turn on xiangshan-nanhu scheduling.
Not strictly a regression, but a bugfix and highly isolated to the
xiangshan-nanhu tuning in the RISC-V backend. So I'm gating this into
gcc-15, assuming pre-commit doesn't balk.
Jeff
diff --git a/gcc/config/riscv/xiangshan.md b/gcc/config/riscv/xiangshan.md
index eb83bbff1be..5ed6bacdd70 100644
--- a/gcc/config/riscv/xiangshan.md
+++ b/gcc/config/riscv/xiangshan.md
@@ -98,6 +98,18 @@ (define_insn_reservation "xiangshan_alu" 1
(eq_attr "type"
"nop,const,branch,arith,shift,slt,multi,logical,move,bitmanip,unknown"))
"xs_alu_rs")
+;; Someone familiar with the xiangshan uarch needs to put
+;; these into the right reservations. This is just a placeholder
+;; for everything I found that had no mapping to a reservation.
+;;
+;; Note that even if the processor does not implementat a particular
+;; instruction it should still have suitable reservations, even if
+;; they are just dummies like this one.
+(define_insn_reservation "xiangshan_alu_unknown" 1
+ (and (eq_attr "tune" "xiangshan")
+ (eq_attr "type"
"zicond,min,max,minu,maxu,clz,ctz,cpop,ghost,rotate,clmul,condmove,crypto,mvpair,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,vsetvl,vsetvl_pre,vlde,vste,vldm,vstm,vlds,vsts,vldux,vldox,vstux,vstox,vldff,vldr,vstr,vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,vssegtux,vssegtox,vlsegdff,vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax,vimul,vidiv,viwmul,vimuladd,sf_vqmacc,viwmuladd,vimerge,vimov,vsalu,vaalu,vsmul,vsshift,vnclip,sf_vfnrclip,vfalu,vfwalu,vfmul,vfdiv,vfwmul,vfmuladd,vfwmuladd,vfsqrt,vfrecp,vfcmp,vfminmax,vfsgnj,vfclass,vfmerge,vfmov,vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,vired,viwred,vfredu,vfredo,vfwredu,vfwredo,vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,vfmovvf,vfmovfv,vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,vgather,vcompress,vmov,vector,vandn,vbrev,vbrev8,vrev8,vclz,vctz,vcpop,vrol,vror,vwsll,vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c,vfncvtbf16,vfwcvtbf16,vfwmaccbf16"))
+ "xs_alu_rs")
+
;; ----------------------------------------------------
;; Float
;; ----------------------------------------------------
diff --git a/gcc/testsuite/gcc.target/riscv/pr114442.c
b/gcc/testsuite/gcc.target/riscv/pr114442.c
new file mode 100644
index 00000000000..c4ca136fdca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr114442.c
@@ -0,0 +1,3 @@
+/* { dg-do compile } */
+/* { dg-options "-mtune=xiangshan-nanhu" } */
+void foo (void) {}
