Re-reading again I realize I misread cache size from your question with cache line size.
Cache size can be whatever yes. Cache line size must match. But that doesn't change the fact that this patch is correct. Thanks, Tamar ________________________________ From: Tamar Christina Sent: Wednesday, January 15, 2025 2:45 PM To: Xi Ruoyao <xry...@xry111.site>; gcc-patches@gcc.gnu.org <gcc-patches@gcc.gnu.org> Cc: nd <n...@arm.com>; Richard Earnshaw <richard.earns...@arm.com>; ktkac...@gcc.gnu.org <ktkac...@gcc.gnu.org>; Richard Sandiford <richard.sandif...@arm.com> Subject: RE: [PATCH]AArch64: have -mcpu=native detect architecture extensions for unknown non-homogenous systems [PR113257] > -----Original Message----- > From: Xi Ruoyao <xry...@xry111.site> > Sent: Wednesday, January 15, 2025 1:40 PM > To: Tamar Christina <tamar.christ...@arm.com>; gcc-patches@gcc.gnu.org > Cc: nd <n...@arm.com>; Richard Earnshaw <richard.earns...@arm.com>; > ktkac...@gcc.gnu.org; Richard Sandiford <richard.sandif...@arm.com> > Subject: Re: [PATCH]AArch64: have -mcpu=native detect architecture extensions > for unknown non-homogenous systems [PR113257] > > On Wed, 2025-01-15 at 13:34 +0000, Tamar Christina wrote: > > > > > > > -----Original Message----- > > > From: Xi Ruoyao <xry...@xry111.site> > > > Sent: Wednesday, January 15, 2025 1:29 PM > > > To: Tamar Christina <tamar.christ...@arm.com>; gcc-patches@gcc.gnu.org > > > Cc: nd <n...@arm.com>; Richard Earnshaw <richard.earns...@arm.com>; > > > ktkac...@gcc.gnu.org; Richard Sandiford <richard.sandif...@arm.com> > > > Subject: Re: [PATCH]AArch64: have -mcpu=native detect architecture > extensions > > > for unknown non-homogenous systems [PR113257] > > > > > > On Sat, 2025-01-11 at 15:18 +0000, Tamar Christina wrote: > > > > However the same thing works for big.LITTLE as in such system the cores > must > > > > have the same extensions otherwise it doesn't fundamentally work. > > > > > > > > i.e. task migration from one core to the other wouldn't work. > > > > > > See https://gcc.gnu.org/PR111768 for a potential issue. > > > > > > > There's no issue there. > > As Alexander says in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111768#c7 > > > > It is not practical for you to have two CPUs in the same system with > > different > capabilities. > > Your kernel will not work, or you have to disable task migration. > > > > The same extends to cache sizes and other properties of the CPU. > > On Intel CPUs it's common that the L1 cache size is different on P and E > cores. The generated code still works but it may be suboptimal if it's > compiled on an E core but the executed on a P core or vice versa. > > Is it different on AArch64? I'd be really surprised if big and LITTLE > must have the same L1 cache size... Yes, Because if the sizes mismatch you break data cache operations. One example is DC ZVA [1] Where the operation clears whole cachelines at a time. This value is cached when doing a long clear operation, such as large memset of 0. Technically speaking the size of VA doesn't have to match the cache size, but practically it always does since otherwise the operation is a lot less efficient. This is an assumption also made in e.g. glibc's memset. If you migrate tasks between the reading of the value and the end of the set you may end up overwriting or not clearing enough. In addition, the Linux kernel will report the smallest value over all the cores so that software gets a coherent value: [2], because again, software can't work effectively when the sizes don't match. And lastly the big.LITTLE programming model explicitly states that the cores must be coherent [3]. This patch does not change the cache sizes anyway as those are determined by the generic cost model, which are a conservative safe minimum that work on all Arm cores. But coherency property is also what dictates that the patch is correct, because as a requirement of big.LITTLE you must be able to seamlessly transfer a program from one core to another. This cannot happen if they vary in capabilities. Regards, Tamar [1] https://developer.arm.com/documentation/102670/0301/AArch64-registers/AArch64-register-descriptions/AArch64-System-instruction-register-description/DC-ZVA--Data-Cache-Zero-by-VA [2] https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1227904.html [3] https://developer.arm.com/documentation/dai0424/a/Power-down-and-power-up-considerations/High-level-considerations/Coherency-in-a-big-LITTLE-system > > > As an aside, today the big.LITTLE selection already enforces a uniform > > feature set. > > -- > Xi Ruoyao <xry...@xry111.site> > School of Aerospace Science and Technology, Xidian University
