Hi,
in PR118154 we emit strided stores but the first of those does not
always have the proper VTYPE. That's because we assume it only
demands an SEW/LMUL ratio rather than the proper SEW and LMUL and
subsequently optimize away the accompanying vsetvl.
This patch corrects the ratio attribute for strided loads and stores.
Regtested on rv64gcv_zvl512b.
Regards
Robin
PR target/118154
gcc/ChangeLog:
* config/riscv/vector.md: Do not return a ratio for strided
loads and stores.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr118154-1.c: New test.
* gcc.target/riscv/rvv/autovec/pr118154-2.c: New test.
---
gcc/config/riscv/vector.md | 5 ++-
.../gcc.target/riscv/rvv/autovec/pr118154-1.c | 23 ++++++++++++++
.../gcc.target/riscv/rvv/autovec/pr118154-2.c | 31 +++++++++++++++++++
3 files changed, 58 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr118154-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr118154-2.c
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index e78d1090696..05a0aed8add 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -471,7 +471,7 @@ (define_attr "vlmul" ""
;; It is valid for instruction that require sew/lmul ratio.
(define_attr "ratio" ""
- (cond [(eq_attr "type" "vimov,vfmov,vldux,vldox,vstux,vstox,\
+ (cond [(eq_attr "type" "vimov,vfmov,vldux,vldox,vstux,vstox,vsts,\
vialu,vshift,vicmp,vimul,vidiv,vsalu,\
vext,viwalu,viwmul,vicalu,vnshift,\
vimuladd,vimerge,vaalu,vsmul,vsshift,\
@@ -494,6 +494,9 @@ (define_attr "ratio" ""
vlsegdff,vssegtux,vlsegdox,vlsegdux")
(match_test "TARGET_XTHEADVECTOR"))
(const_int INVALID_ATTRIBUTE)
+ (and (eq_attr "type" "vlds")
+ (match_test "VECTOR_MODE_P (GET_MODE (operands[3]))"))
+ (const_int INVALID_ATTRIBUTE)
(eq_attr "mode" "RVVM8QI,RVVM1BI") (const_int 1)
(eq_attr "mode" "RVVM4QI,RVVMF2BI") (const_int 2)
(eq_attr "mode" "RVVM2QI,RVVMF4BI") (const_int 4)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr118154-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr118154-1.c
new file mode 100644
index 00000000000..55386568a5f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr118154-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target riscv_v_ok } */
+/* { dg-add-options riscv_v } */
+/* { dg-additional-options "-std=gnu99 -Wno-pedantic" } */
+
+long a;
+char b;
+char c[22][484];
+int main() {
+ for (int e = 4; e < 33; e++) {
+ for (int f = 0; f < 3; f++)
+ for (int g = 0; g < 18; g++) {
+ c[f][g * 22] = 1;
+ a = ({ a > 1 ? a : 1; });
+ }
+ for (int i = 0; i < 33; i++)
+ for (int h = 0; h < 6; h++)
+ for (int j = 0; j < 17; j++)
+ b = ({ b > 17 ? b : 17; });
+ }
+ if (c[1][44] != 1)
+ __builtin_abort ();
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr118154-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr118154-2.c
new file mode 100644
index 00000000000..4172f292994
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr118154-2.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-require-effective-target riscv_v_ok } */
+/* { dg-add-options riscv_v } */
+/* { dg-additional-options "-std=gnu99 -Wno-pedantic" } */
+
+long a;
+signed char b;
+long long d;
+signed char c[22][22][484];
+void m(long long *l, int n) { *l ^= n + (*l >> 2); }
+int main() {
+ signed char l = 35;
+ for (signed char f = 4; f; f++) {
+ for (signed g = 0; g < 022; g += 4)
+ for (signed char h = 0; h < 022; h++) {
+ c[9][g][h * 22 + h] = l;
+ a = ({ a > 4095 ? a : 4095; });
+ }
+ for (int i = 0; i < 22; i += 3)
+ for (signed char j = 1; j; j++)
+ for (signed char k = 0; k < 022; k++)
+ b = ({ b > 19 ? b : 19; });
+ }
+ for (long f = 0; f < 22; ++f)
+ for (long g = 0; g < 22; ++g)
+ for (long h = 0; h < 22; ++h)
+ for (long i = 0; i < 22; ++i)
+ m(&d, c[f][g][h * 2 + i]);
+ if (d != 38)
+ __builtin_abort ();
+}
--
2.47.1
