On Tue, Jan 07, 2025 at 07:55:45AM -0800, Palmer Dabbelt wrote: > On Mon, 09 Dec 2024 08:13:22 PST (-0800), dimi...@dinux.eu wrote: > > Many test cases implicitly require some form of I ABI variant for > > RISC-V to be the default. Hence they fail when ILP32E is configured as > > the default ABI for the toolchain. Example error: > > > > spawn ... -march=rv32gc_zbb ... > > cc1: error: ILP32E ABI does not support the 'D' extension > > > > This patch series adds explicit RISC-V ABI configuration to the test > > cases, in order to remove spurious errors for RV32E toolchain. My end > > goal is to start running bi-monthly regression tests for RV32E, and > > publish to gcc-testretults. > > > > My understanding is that RV32E is a popular choice for low-end > > microcontrollers, and is here to stay. The existing RV32I test runs > > achieve somewhat limited coverage for RV32E. So running regression > > tests for RV32E should be beneficial for the community. > > Thanks for doing this. This came up in the patchwork meeting, but I'm not > actually sure how widely used the E ISAs are. That's why they don't get the > testing bandwidth that some of the other sub-targets do, and thus why these > sorts of bugs linger.
I don't know the market share for E ISAs, either. I simply noticed that it is used in some ultra low cost microcontrollers (e.g. CH32V003 in https://www.olimex.com/Products/Retro-Computers/RVPC/open-source-hardware). > > So if you're interested in E and want to test it that's great, it's just the > sort of thing that needs someone who cares to make sure specific sub-targets > stay clean. You just might be in for a bit of an uphill battle, though, as > there's a ton of RISC-V sub-targets so these uncommon ones don't get as much > love. I don't anticipate a huge number of regressions. So the effort required to monitor and fix those should fit in my hobby time budget. > > If you've got some specific E sub-targets you're interested in then we > should probably get them added to CI, though we're in a bit of a CI > resourcing crunch right now so it might be a slower process than normal... I do not expect E targets to be added to RISE CI because I don't want to distract the main RISC-V efforts. I'm perfectly happy to run the E ISA testsuite on my PC. I'll start only with RV32EC sub-target for now. Regards, Dimitar > > I think Jeff already said something (they're at least marked as "Accepted" > in patchwork), but > > Acked-by: Palmer Dabbelt <pal...@rivosinc.com> > > if that helps any. Thanks! >
