From: yulong <shiyul...@iscas.ac.cn> This patch implements the Sifvie vendor extension Xsfvfnrclipxfqf[1] support to gcc. Providing support for FP32-to-int8 Ranged Clip instrctions.
[1] https://www.sifive.com/document-file/sifive-vector-coprocessor-interface-vcix-software Co-Authored by: Jiawei Chen <jia...@iscas.ac.cn> Co-Authored by: Shihua Liao <shi...@iscas.ac.cn> Co-Authored by: Yixuan Chen <chenyix...@iscas.ac.cn> Diff with V2: Change the RTL mode from unspec to unspec_volatile. Liao Shihua (1): RISC-V: Add intrinsic testcases for SiFive Xsfvcp extensions. yulong (1): RISC-V: Add intrinsics support for SiFive Xsfvcp extensions. gcc/config/riscv/constraints.md | 10 + gcc/config/riscv/generic-vector-ooo.md | 4 + gcc/config/riscv/genrvv-type-indexer.cc | 9 + .../riscv/riscv-vector-builtins-shapes.cc | 48 ++ .../riscv/riscv-vector-builtins-shapes.h | 2 + .../riscv/riscv-vector-builtins-types.def | 40 ++ gcc/config/riscv/riscv-vector-builtins.cc | 362 ++++++++++- gcc/config/riscv/riscv-vector-builtins.def | 30 +- gcc/config/riscv/riscv-vector-builtins.h | 8 + gcc/config/riscv/riscv.md | 5 +- .../riscv/sifive-vector-builtins-bases.cc | 78 +++ .../riscv/sifive-vector-builtins-bases.h | 3 + .../sifive-vector-builtins-functions.def | 45 ++ gcc/config/riscv/sifive-vector.md | 569 ++++++++++++++++++ gcc/config/riscv/vector-iterators.md | 48 ++ gcc/config/riscv/vector.md | 3 +- .../gcc.target/riscv/rvv/xsfvector/sf_vc_f.c | 88 +++ .../gcc.target/riscv/rvv/xsfvector/sf_vc_i.c | 132 ++++ .../gcc.target/riscv/rvv/xsfvector/sf_vc_v.c | 107 ++++ .../gcc.target/riscv/rvv/xsfvector/sf_vc_x.c | 138 +++++ 20 files changed, 1722 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_v.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_x.c -- 2.34.1
