A recent bugfix (eee2891312) for PR117830 also addressed PR118149. This patch adds two test cases for PR118149. These tests are different than other tests in that one of the vec-perm selectors contains indices in descending order (1, 1, 0, 0), which is the root cause for the ICE observed in PR118149.
PR 118149 gcc/testsuite/ChangeLog: * gcc.dg/tree-ssa/pr118149-2.c: New test. * gcc.dg/tree-ssa/pr118149.c: New test. Signed-off-by: Christoph Müllner <christoph.muell...@vrull.eu> --- gcc/testsuite/gcc.dg/tree-ssa/pr118149-2.c | 37 ++++++++++++++++++++++ gcc/testsuite/gcc.dg/tree-ssa/pr118149.c | 20 ++++++++++++ 2 files changed, 57 insertions(+) create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr118149-2.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr118149.c diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr118149-2.c b/gcc/testsuite/gcc.dg/tree-ssa/pr118149-2.c new file mode 100644 index 00000000000..31f3d7e0dc7 --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr118149-2.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -fdump-tree-forwprop1-details -Wno-psabi" } */ +/* { dg-additional-options "-msse2" { target i?86-*-* x86_64-*-* } } */ + +typedef int vec __attribute__((vector_size (4 * sizeof (float)))); + +void f1 (vec *p_v_in, vec *p_v_out_1, vec *p_v_out_2) +{ + vec sel00 = { 1, 1, 3, 3 }; + vec sel01 = { 0, 0, 2, 2 }; + vec sel10 = { 3, 3, 2, 2 }; + vec sel11 = { 1, 1, 0, 0 }; + vec sel = { 0, 1, 6, 7 }; + vec v_1, v_2, v_x, v_y, v_out_1, v_out_2; + vec v_in = *p_v_in; + + /* First vec perm sequence. */ + v_1 = __builtin_shuffle (v_in, v_in, sel00); + v_2 = __builtin_shuffle (v_in, v_in, sel01); + v_x = v_2 - v_1; + v_y = v_1 + v_2; + v_out_1 = __builtin_shuffle (v_y, v_x, sel); + + /* Second vec perm sequence. */ + v_1 = __builtin_shuffle (v_in, v_in, sel10); + v_2 = __builtin_shuffle (v_in, v_in, sel11); + v_x = v_2 - v_1; + v_y = v_1 + v_2; + v_out_2 = __builtin_shuffle (v_y, v_x, sel); + + *p_v_out_1 = v_out_1; + *p_v_out_2 = v_out_2; +} + +/* { dg-final { scan-tree-dump "Vec perm simplify sequences have been blended" "forwprop1" { target { aarch64*-*-* i?86-*-* x86_64-*-* } } } } */ +/* { dg-final { scan-tree-dump "VEC_PERM_EXPR.*{ 0, 0, 6, 6 }" "forwprop1" { target { aarch64*-*-* i?86-*-* x86_64-*-* } } } } */ +/* { dg-final { scan-tree-dump "VEC_PERM_EXPR.*{ 1, 1, 7, 7 }" "forwprop1" { target { aarch64*-*-* i?86-*-* x86_64-*-* } } } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr118149.c b/gcc/testsuite/gcc.dg/tree-ssa/pr118149.c new file mode 100644 index 00000000000..f471877f661 --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr118149.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -fdump-tree-forwprop4-details -Wno-psabi" } */ +/* { dg-additional-options "-msse2" { target i?86-*-* x86_64-*-* } } */ + +float *fastconv_parse_dst; + +void fastconv_parse () +{ + float r3k = fastconv_parse_dst[1] - fastconv_parse_dst[3], + i0k = fastconv_parse_dst[4] + fastconv_parse_dst[6], + i1k = fastconv_parse_dst[4] - fastconv_parse_dst[6], + i2k = fastconv_parse_dst[5] + fastconv_parse_dst[7]; + fastconv_parse_dst[1] = fastconv_parse_dst[0]; + fastconv_parse_dst[4] = fastconv_parse_dst[5] = i0k - i2k; + fastconv_parse_dst[6] = fastconv_parse_dst[7] = i1k + r3k; +} + +/* { dg-final { scan-tree-dump "Vec perm simplify sequences have been blended" "forwprop4" { target { aarch64*-*-* i?86-*-* x86_64-*-* } } } } */ +/* { dg-final { scan-tree-dump "VEC_PERM_EXPR.*{ 0, 0, 6, 6 }" "forwprop4" { target { aarch64*-*-* i?86-*-* x86_64-*-* } } } } */ +/* { dg-final { scan-tree-dump "VEC_PERM_EXPR.*{ 1, 1, 7, 7 }" "forwprop4" { target { aarch64*-*-* i?86-*-* x86_64-*-* } } } } */ -- 2.47.1