[SPARC] Fix PR target/118096

[Eric Botcazou]

This replaces the use of FAIL in the new vec_cmp[u] expanders by that of a 
predicate for the operator, which is (apparently) required for the optabs 
machinery to properly compute the set of supported vector comparisons.

Tested on SPARC64/Solaris 11.4, applied on the mainline.


2024-12-18  Eric Botcazou  <ebotca...@adacore.com>

        PR target/118096
        * config/sparc/predicates.md (vec_cmp_operator): New predicate.
        (vec_cmpu_operator): Likewise.
        * config/sparc/sparc.md (vec_cmp<FPCMP:mode><P:mode>): Use the
        vec_cmp_operator predicate instead of FAILing the expansion.
        (vec_cmpu<FPCMP:mode><P:mode>): Likewise for vec_cmpu_operator.
 
-- 
Eric Botcazou
diff --git a/gcc/config/sparc/predicates.md b/gcc/config/sparc/predicates.md
index 1be76a62f57..067659b0ce2 100644
--- a/gcc/config/sparc/predicates.md
+++ b/gcc/config/sparc/predicates.md
@@ -527,3 +527,37 @@
 ;; and (xor ... (not ...)) to (not (xor ...)).
 (define_predicate "cc_arith_not_operator"
   (match_code "and,ior"))
+
+;; Return true if OP is an operator for a vec_cmp pattern
+;; VIS 4 is required for ordering comparisons if the mode is V8QI
+(define_predicate "vec_cmp_operator"
+  (match_operand 0 "comparison_operator")
+{
+  const enum rtx_code code = GET_CODE (op);
+
+  switch (GET_MODE (XEXP (op, 0)))
+    {
+    case V8QImode:
+      return code == EQ || code == NE || TARGET_VIS4;
+
+    default:
+      return true;
+    }
+})
+
+;; Return true if OP is an operator for a vec_cmpu pattern
+;; VIS 4 is required for ordering comparisons if the mode is not V8QI
+(define_predicate "vec_cmpu_operator"
+  (match_operand 0 "comparison_operator")
+{
+  const enum rtx_code code = GET_CODE (op);
+
+  switch (GET_MODE (XEXP (op, 0)))
+    {
+    case V8QImode:
+      return true;
+
+    default:
+      return code == EQ || code == NE || TARGET_VIS4;
+    }
+})
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 159518d4b8f..1d78172571c 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -9000,17 +9000,13 @@
 
 (define_expand "vec_cmp<FPCMP:mode><P:mode>"
   [(set (match_operand:P 0 "register_operand" "")
-        (match_operator:P 1 "comparison_operator"
+        (match_operator:P 1 "vec_cmp_operator"
           [(match_operand:FPCMP 2 "register_operand" "")
            (match_operand:FPCMP 3 "register_operand" "")]))]
   "TARGET_VIS3"
 {
   enum rtx_code code = GET_CODE (operands[1]);
 
-  /* VIS 4 is required for ordering comparisons if the mode is V8QI.  */
-  if (<FPCMP:MODE>mode == V8QImode && code != EQ && code != NE && !TARGET_VIS4)
-    FAIL;
-
   if (code == LT || code == GE)
     {
       PUT_CODE (operands[1], swap_condition (code));
@@ -9028,17 +9024,13 @@
 
 (define_expand "vec_cmpu<FPCMP:mode><P:mode>"
   [(set (match_operand:P 0 "register_operand" "")
-        (match_operator:P 1 "comparison_operator"
+        (match_operator:P 1 "vec_cmpu_operator"
           [(match_operand:FPCMP 2 "register_operand" "")
            (match_operand:FPCMP 3 "register_operand" "")]))]
   "TARGET_VIS3"
 {
   enum rtx_code code = GET_CODE (operands[1]);
 
-  /* VIS 4 is required for ordering comparisons if the mode is not V8QI.  */
-  if (<FPCMP:MODE>mode != V8QImode && code != EQ && code != NE && !TARGET_VIS4)
-    FAIL;
-
   if (code == LTU || code == GEU)
     {
       PUT_CODE (operands[1], swap_condition (code));