Richard Biener <richard.guent...@gmail.com> writes:
> On Mon, Dec 9, 2024 at 11:54 PM Richard Sandiford
> <richard.sandif...@arm.com> wrote:
>>
>> This patch removes the remaining traces of the vcond{,u,eq} optabs.
>> Earlier patches removed the target-independent uses and I couldn't
>> find any direct references to either the *_optabs or the ifns
>> in target-specific code.
>>
>> Tested on aarch64-linux-gnu. OK to install?
>
> OK. Existing (define_expand "vcond...") will still "work", aka this
> doesn't break their compile because of some checking against
> known optab names?
Yeah, that's right. Any pattern not beginning with "*" will get
the usual gen_* routine, and any patterns using "@" will get the
routines associate with "@". It isn't keyed off whether the
pattern is a well-known name.
Thanks,
Richard
> Thanks,
> Richard.
>
>> Richard
>>
>>
>> gcc/
>> * doc/md.texi (vcond@var{m}@var{n}, vcondu@var{m}@var{n})
>> (vcondeq@var{m}@var{n}): Delete.
>> (vcond_mask_@var{m}@var{n}): Redocument in standalone form.
>> * internal-fn.def (VCOND, VCONDU, VCONDEQ): Delete.
>> * internal-fn.cc (expand_vec_cond_optab_fn): Delete.
>> * optabs.def (vcond_optab, vcondu_optab, vcondeq_optab): Delete.
>> ---
>> gcc/doc/md.texi | 46 +++++++++++++++++----------------------
>> gcc/internal-fn.cc | 52 ---------------------------------------------
>> gcc/internal-fn.def | 3 ---
>> gcc/optabs.def | 3 ---
>> 4 files changed, 20 insertions(+), 84 deletions(-)
>>
>> diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
>> index 69605bf75c0..f0b63a144ad 100644
>> --- a/gcc/doc/md.texi
>> +++ b/gcc/doc/md.texi
>> @@ -5297,34 +5297,28 @@ or @code{vec_cmpu@var{m}@var{n}} instruction pattern
>> is supported,
>> it will be preferred over @code{vec_cmpeq@var{m}@var{n}}, so there is
>> no need to define this instruction pattern if the others are supported.
>>
>> -@cindex @code{vcond@var{m}@var{n}} instruction pattern
>> -@item @samp{vcond@var{m}@var{n}}
>> -Output a conditional vector move. Operand 0 is the destination to
>> -receive a combination of operand 1 and operand 2, which are of mode @var{m},
>> -dependent on the outcome of the predicate in operand 3 which is a signed
>> -vector comparison with operands of mode @var{n} in operands 4 and 5. The
>> -modes @var{m} and @var{n} should have the same size. Operand 0
>> -will be set to the value @var{op1} & @var{msk} | @var{op2} & ~@var{msk}
>> -where @var{msk} is computed by element-wise evaluation of the vector
>> -comparison with a truth value of all-ones and a false value of all-zeros.
>> -
>> -@cindex @code{vcondu@var{m}@var{n}} instruction pattern
>> -@item @samp{vcondu@var{m}@var{n}}
>> -Similar to @code{vcond@var{m}@var{n}} but performs unsigned vector
>> -comparison.
>> -
>> -@cindex @code{vcondeq@var{m}@var{n}} instruction pattern
>> -@item @samp{vcondeq@var{m}@var{n}}
>> -Similar to @code{vcond@var{m}@var{n}} but performs equality or
>> -non-equality vector comparison only. If @code{vcond@var{m}@var{n}}
>> -or @code{vcondu@var{m}@var{n}} instruction pattern is supported,
>> -it will be preferred over @code{vcondeq@var{m}@var{n}}, so there is
>> -no need to define this instruction pattern if the others are supported.
>> -
>> @cindex @code{vcond_mask_@var{m}@var{n}} instruction pattern
>> @item @samp{vcond_mask_@var{m}@var{n}}
>> -Similar to @code{vcond@var{m}@var{n}} but operand 3 holds a pre-computed
>> -result of vector comparison.
>> +Output a conditional vector move. Operand 0 is the destination to
>> +receive a combination of operand 1 and operand 2, depending on the
>> +mask in operand 3. Operands 0, 1, and 2 have mode @var{m} while
>> +operand 3 has mode @var{n}.
>> +
>> +Suppose that @var{m} has @var{e} elements. There are then two
>> +supported forms of @var{n}. The first form is an integer or
>> +boolean vector that also has @var{e} elements. In this case, each
>> +element is -1 or 0, with -1 selecting elements from operand 1 and
>> +0 selecting elements from operand 2. The second supported form
>> +of @var{n} is a scalar integer that has at least @var{e} bits.
>> +A set bit then selects from operand 1 and a clear bit selects
>> +from operand 2. Bits @var{e} and above have no effect.
>> +
>> +Subject to those restrictions, the behavior is equivalent to:
>> +
>> +@smallexample
>> +for (i = 0; i < @var{e}; i++)
>> + op0[i] = op3[i] ? op1[i] : op2[i];
>> +@end smallexample
>>
>> @cindex @code{vcond_mask_len_@var{m}@var{n}} instruction pattern
>> @item @samp{vcond_mask_len_@var{m}@var{n}}
>> diff --git a/gcc/internal-fn.cc b/gcc/internal-fn.cc
>> index 8bafbc4c935..56e9ded7e85 100644
>> --- a/gcc/internal-fn.cc
>> +++ b/gcc/internal-fn.cc
>> @@ -3138,58 +3138,6 @@ expand_partial_store_optab_fn (internal_fn ifn, gcall
>> *stmt, convert_optab optab
>> #define expand_len_store_optab_fn expand_partial_store_optab_fn
>> #define expand_mask_len_store_optab_fn expand_partial_store_optab_fn
>>
>> -/* Expand VCOND, VCONDU and VCONDEQ optab internal functions.
>> - The expansion of STMT happens based on OPTAB table associated. */
>> -
>> -static void
>> -expand_vec_cond_optab_fn (internal_fn, gcall *stmt, convert_optab optab)
>> -{
>> - class expand_operand ops[6];
>> - insn_code icode;
>> - tree lhs = gimple_call_lhs (stmt);
>> - tree op0a = gimple_call_arg (stmt, 0);
>> - tree op0b = gimple_call_arg (stmt, 1);
>> - tree op1 = gimple_call_arg (stmt, 2);
>> - tree op2 = gimple_call_arg (stmt, 3);
>> - enum tree_code tcode = (tree_code) int_cst_value (gimple_call_arg (stmt,
>> 4));
>> -
>> - tree vec_cond_type = TREE_TYPE (lhs);
>> - tree op_mode = TREE_TYPE (op0a);
>> - bool unsignedp = TYPE_UNSIGNED (op_mode);
>> -
>> - machine_mode mode = TYPE_MODE (vec_cond_type);
>> - machine_mode cmp_op_mode = TYPE_MODE (op_mode);
>> -
>> - icode = convert_optab_handler (optab, mode, cmp_op_mode);
>> - rtx comparison
>> - = vector_compare_rtx (VOIDmode, tcode, op0a, op0b, unsignedp, icode, 4);
>> - /* vector_compare_rtx legitimizes operands, preserve equality when
>> - expanding op1/op2. */
>> - rtx rtx_op1, rtx_op2;
>> - if (operand_equal_p (op1, op0a))
>> - rtx_op1 = XEXP (comparison, 0);
>> - else if (operand_equal_p (op1, op0b))
>> - rtx_op1 = XEXP (comparison, 1);
>> - else
>> - rtx_op1 = expand_normal (op1);
>> - if (operand_equal_p (op2, op0a))
>> - rtx_op2 = XEXP (comparison, 0);
>> - else if (operand_equal_p (op2, op0b))
>> - rtx_op2 = XEXP (comparison, 1);
>> - else
>> - rtx_op2 = expand_normal (op2);
>> -
>> - rtx target = expand_expr (lhs, NULL_RTX, VOIDmode, EXPAND_WRITE);
>> - create_call_lhs_operand (&ops[0], target, mode);
>> - create_input_operand (&ops[1], rtx_op1, mode);
>> - create_input_operand (&ops[2], rtx_op2, mode);
>> - create_fixed_operand (&ops[3], comparison);
>> - create_fixed_operand (&ops[4], XEXP (comparison, 0));
>> - create_fixed_operand (&ops[5], XEXP (comparison, 1));
>> - expand_insn (icode, 6, ops);
>> - assign_call_lhs (lhs, target, &ops[0]);
>> -}
>> -
>> /* Expand VCOND_MASK optab internal function.
>> The expansion of STMT happens based on OPTAB table associated. */
>>
>> diff --git a/gcc/internal-fn.def b/gcc/internal-fn.def
>> index 6e84c693697..54149b66537 100644
>> --- a/gcc/internal-fn.def
>> +++ b/gcc/internal-fn.def
>> @@ -237,9 +237,6 @@ DEF_INTERNAL_OPTAB_FN (MASK_STORE_LANES, 0,
>> DEF_INTERNAL_OPTAB_FN (MASK_LEN_STORE_LANES, 0,
>> vec_mask_len_store_lanes, mask_store_lanes)
>>
>> -DEF_INTERNAL_OPTAB_FN (VCOND, ECF_CONST | ECF_NOTHROW, vcond, vec_cond)
>> -DEF_INTERNAL_OPTAB_FN (VCONDU, ECF_CONST | ECF_NOTHROW, vcondu, vec_cond)
>> -DEF_INTERNAL_OPTAB_FN (VCONDEQ, ECF_CONST | ECF_NOTHROW, vcondeq, vec_cond)
>> DEF_INTERNAL_OPTAB_FN (VCOND_MASK, ECF_CONST | ECF_NOTHROW,
>> vcond_mask, vec_cond_mask)
>> DEF_INTERNAL_OPTAB_FN (VCOND_MASK_LEN, ECF_CONST | ECF_NOTHROW,
>> diff --git a/gcc/optabs.def b/gcc/optabs.def
>> index 5d75b1379ac..eda8af01b16 100644
>> --- a/gcc/optabs.def
>> +++ b/gcc/optabs.def
>> @@ -93,9 +93,6 @@ OPTAB_CD(vec_mask_load_lanes_optab,
>> "vec_mask_load_lanes$a$b")
>> OPTAB_CD(vec_mask_store_lanes_optab, "vec_mask_store_lanes$a$b")
>> OPTAB_CD(vec_mask_len_load_lanes_optab, "vec_mask_len_load_lanes$a$b")
>> OPTAB_CD(vec_mask_len_store_lanes_optab, "vec_mask_len_store_lanes$a$b")
>> -OPTAB_CD(vcond_optab, "vcond$a$b")
>> -OPTAB_CD(vcondu_optab, "vcondu$a$b")
>> -OPTAB_CD(vcondeq_optab, "vcondeq$a$b")
>> OPTAB_CD(vcond_mask_optab, "vcond_mask_$a$b")
>> OPTAB_CD(vec_cmp_optab, "vec_cmp$a$b")
>> OPTAB_CD(vec_cmpu_optab, "vec_cmpu$a$b")
>> --
>> 2.25.1
>>
