On 12/9/24 10:00 AM, Richard Sandiford wrote:
Mariam Arutunian <mariamarutun...@gmail.com> writes:
Hello,
This patch series is a revised version of the following:
https://gcc.gnu.org/pipermail/gcc-patches/2024-November/668229.html.
In this version:
- Patch 09/12 has been updated with comments provided by Matevos, which
were missing in the previously submitted series.
- Patch 06/12 includes the following change made by Richard Sandiford,
which is necessary for the code to compile and hasn't been added to the GCC
master branch.
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -4312,7 +4312,7 @@
;; RTL uses GCC vector extension indices throughout so flip only for
assembly.
;; Extracting lane zero is split into a simple move when it is between SIMD
;; registers or a store.
-(define_insn_and_split "aarch64_get_lane<mode>"
+(define_insn_and_split "@aarch64_get_lane<mode>"
[(set (match_operand:<VEL> 0 "aarch64_simd_nonimmediate_operand" "=?r, w,
Utv")
(vec_select:<VEL>
(match_operand:VALL_F16 1 "register_operand" "w, w, w")
Oops, sorry, I misread this and thought that you were waiting for
the above to go in before pushing the aarch64 changes. I now realise
that that wasn't the case, but only after I'd tested the below on
aarch64-linux-gnu & pushed to trunk.
The OK for the aarch64 changes
[https://gcc.gnu.org/pipermail/gcc-patches/2024-August/661047.html]
still stands. Let me know if you'd like me to test & push the changes.
Thanks again for doing this.
Thanks. I was just about to reach out to confirm we're OK on aarch64.
I was going to run everything through one of the cfarm machines or
perhaps my rpi as a final test.
Jeff
