This test would fail if GCC is configured with non-default options,
such as -mtune=cortex-a9.
This 'unexpected' scheduling makes the DLSTP optimization generate
subs lr, #16
bhi .L4
lctp
pop {r4, r5, pc}
.L4:
sub ip, ip, #16
b <loop-begin>
instead of the expected
sub ip, ip, #16
letp lr, <loop-begin>
Although GCC still optimizes all 144 loops, only 96 use letp, 48
others use lctp.
The patch simply forces -mtune=cortex-m55 to avoid this unexpected
issue.
gcc/testsuite/ChangeLog:
* gcc.target/arm/mve/dlstp-compile-asm-1.c: Add -mtune=cortex-m55
---
gcc/testsuite/gcc.target/arm/mve/dlstp-compile-asm-1.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/arm/mve/dlstp-compile-asm-1.c
b/gcc/testsuite/gcc.target/arm/mve/dlstp-compile-asm-1.c
index 6e6da3d3d59..7b7f1da6435 100644
--- a/gcc/testsuite/gcc.target/arm/mve/dlstp-compile-asm-1.c
+++ b/gcc/testsuite/gcc.target/arm/mve/dlstp-compile-asm-1.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-options "-O3 -save-temps" } */
+/* { dg-options "-O3 -save-temps -mtune=cortex-m55" } */
/* { dg-add-options arm_v8_1m_mve } */
#include <arm_mve.h>
--
2.34.1