LGTM, committed to trunk :)
On Mon, Dec 2, 2024 at 9:33 AM <shiyul...@iscas.ac.cn> wrote: > > From: yulong <shiyul...@iscas.ac.cn> > > This patch implements the Sifvie vendor extension Xsfvfnrclipxfqf[1] > support to gcc. Providing support for FP32-to-int8 Ranged Clip > instrctions. > > [1] https://www.sifive.com/document-file/fp32-to-int8-ranged-clip-instructions > > Co-Authored by: Jiawei Chen <jia...@iscas.ac.cn> > Co-Authored by: Shihua Liao <shi...@iscas.ac.cn> > Co-Authored by: Yixuan Chen <chenyix...@iscas.ac.cn> > > yulong (2): > RISC-V: Add intrinsics support for SiFive Xsfvfnrclipxfqf extensions. > RISC-V: Add intrinsics testcases for SiFive Xsfvfnrclipxfqf > extensions. > > gcc/config/riscv/generic-vector-ooo.md | 2 +- > gcc/config/riscv/genrvv-type-indexer.cc | 10 + > .../riscv/riscv-vector-builtins-bases.cc | 6 - > .../riscv/riscv-vector-builtins-bases.h | 6 + > .../riscv/riscv-vector-builtins-shapes.cc | 28 + > .../riscv/riscv-vector-builtins-shapes.h | 1 + > gcc/config/riscv/riscv-vector-builtins.cc | 51 +- > gcc/config/riscv/riscv-vector-builtins.def | 31 +- > gcc/config/riscv/riscv-vector-builtins.h | 7 + > gcc/config/riscv/riscv.md | 3 +- > .../riscv/sifive-vector-builtins-bases.cc | 52 ++ > .../riscv/sifive-vector-builtins-bases.h | 2 + > .../sifive-vector-builtins-functions.def | 4 + > gcc/config/riscv/sifive-vector.md | 20 + > gcc/config/riscv/vector-iterators.md | 30 +- > .../riscv/rvv/xsfvector/sf_vfnrclip_x_f_qf.c | 606 ++++++++++++++++++ > .../riscv/rvv/xsfvector/sf_vfnrclip_xu_f_qf.c | 605 +++++++++++++++++ > 17 files changed, 1425 insertions(+), 39 deletions(-) > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vfnrclip_x_f_qf.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vfnrclip_xu_f_qf.c > > -- > 2.34.1 >
