> On 27 Nov 2024, at 09:34, Richard Sandiford <richard.sandif...@arm.com> wrote: > > Soumya AR <soum...@nvidia.com> writes: >> NBSL, BSL1N, and BSL2N are bit-select intructions on SVE2 with certain >> operands >> inverted. These can be extended to work with Neon modes. >> >> Since these instructions are unpredicated, duplicate patterns were added with >> the predicate removed to generate these instructions for Neon modes. >> >> The patch was bootstrapped and regtested on aarch64-linux-gnu, no regression. >> OK for mainline? >> >> Signed-off-by: Soumya AR <soum...@nvidia.com> >> >> gcc/ChangeLog: >> >> * config/aarch64/aarch64-sve2.md >> (*aarch64_sve2_nbsl_unpred<mode>): New pattern to match unpredicated >> form. >> (*aarch64_sve2_bsl1n_unpred<mode>): Likewise. >> (*aarch64_sve2_bsl2n_unpred<mode>): Likewise. >> >> gcc/testsuite/ChangeLog: >> >> * gcc.target/aarch64/sve/bitsel.c: New test. > > Thanks for the patch. But since this is a new optimisation, and is not > fixing a regression, I'm not sure whether it would be appropriate during > stage 3. Let's see what other maintainers say.
IMO it’s not high risk but it’s a nice-to-have optimisation rather than driven by a concrete motivating workload. Given that we have a few such patches (like the ASRD patch from Soumya) it would be consistent to either take them all now or stage them all for GCC 16. I’d be okay with deferring them to GCC 16 but would appreciate if they received some feedback on the implementation beforehand so they can be polished for next stage1. Thanks, Kyrill > > Richard >
