The test case gcc.target/arm/its.c was created together with restriction
of IT blocks for Cortex-M7. As the test case fails on all tunes that
does not match Cortex-M7, explicitly test it for Cortex-M7. To have some
additional faith that GCC does the correct thing, I also added another
variant of the test for Cortex-M3 that should allow longer IT blocks.
gcc/testsuite/ChangeLog:
PR testsuite/94531
* gcc.target/arm/its.c: Removed.
* gcc.target/arm/its-1.c: Copy of gcc.target/arm/its.c. Use
effective-target arm_cpu_cortex_m7.
* gcc.target/arm/its-2.c: Copy of gcc.target/arm/its.c. Use
effective-target arm_cpu_cortex_m3.
Signed-off-by: Torbjörn SVENSSON <torbjorn.svens...@foss.st.com>
---
.../gcc.target/arm/{its.c => its-1.c} | 7 +++---
gcc/testsuite/gcc.target/arm/its-2.c | 24 +++++++++++++++++++
2 files changed, 28 insertions(+), 3 deletions(-)
rename gcc/testsuite/gcc.target/arm/{its.c => its-1.c} (67%)
create mode 100644 gcc/testsuite/gcc.target/arm/its-2.c
diff --git a/gcc/testsuite/gcc.target/arm/its.c
b/gcc/testsuite/gcc.target/arm/its-1.c
similarity index 67%
rename from gcc/testsuite/gcc.target/arm/its.c
rename to gcc/testsuite/gcc.target/arm/its-1.c
index f81a0df51cd..78323b89892 100644
--- a/gcc/testsuite/gcc.target/arm/its.c
+++ b/gcc/testsuite/gcc.target/arm/its-1.c
@@ -1,7 +1,8 @@
/* { dg-do compile } */
-/* { dg-require-effective-target arm_cortex_m } */
-/* { dg-require-effective-target arm_thumb2 } */
+/* { dg-require-effective-target arm_cpu_cortex_m7_ok } */
/* { dg-options "-O2" } */
+/* { dg-add-options arm_cpu_cortex_m7 } */
+
int test (int a, int b)
{
int r;
@@ -21,4 +22,4 @@ int test (int a, int b)
}
/* Ensure there is no IT block with more than 2 instructions, ie. we only allow
IT, ITT and ITE. */
-/* { dg-final { scan-assembler-not "\\sit\[te\]{2}" } } */
+/* { dg-final { scan-assembler-not "\tit\[te\]{2}" } } */
diff --git a/gcc/testsuite/gcc.target/arm/its-2.c
b/gcc/testsuite/gcc.target/arm/its-2.c
new file mode 100644
index 00000000000..9eb3bf5ce8c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/its-2.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_cpu_cortex_m3_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_cpu_cortex_m3 } */
+
+int test (int a, int b)
+{
+ int r;
+ if (a > 10)
+ {
+ r = a - b;
+ r += 10;
+ }
+ else
+ {
+ r = b - a;
+ r -= 7;
+ }
+ if (r > 0)
+ r -= 3;
+ return r;
+}
+/* Ensure there is an IT block with at least 2 instructions. */
+/* { dg-final { scan-assembler "\tit\[te\]{2}" } } */
--
2.25.1
