From: Szabolcs Nagy <szabolcs.n...@arm.com>
Add instructions for the Guarded Control Stack extension.
GCSSS1 and GCSSS2 are always used together in the compiler and an extra
"mov xn, 0" should be always added before GCSSS2 to clear the output
register. This is needed to get reasonable result when GCS is disabled,
when these instructions are NOPs. Since the instructions are expected
to be used behind runtime feature checks, this is mainly relevant if
GCS can be disabled asynchronously.
GCSPOPM does not have embedded move and code code that emits this
instruction must first emit a zeroing of operand 1 to get a reasonable
result when GCS is not enabled.
The output of GCSPOPM is usually not needed, so a separate gcspopm_xzr
was added to model that. Did not do the same for GCSSS as it is a less
common operation.
The used mnemonics do not depend on updated assembler since these
instructions can be used without new -march setting behind a runtime
check.
Reading the GCSPR is modelled as unspec_volatile so it does not get
reordered wrt the other instructions changing the GCSPR.
gcc/ChangeLog:
* config/aarch64/aarch64.md (aarch64_load_gcspr): New.
(aarch64_gcspopm): New.
(aarch64_gcspopm_xzr): New.
(aarch64_gcsss1): New.
(aarch64_gcsss2): New.
Co-authored-by: Richard Sandiford <richard.sandif...@arm.com>
---
gcc/config/aarch64/aarch64.md | 39 +++++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 0c5694f3e5e..e16e841fae0 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -382,6 +382,10 @@ (define_c_enum "unspecv" [
UNSPECV_BTI_J ; Represent BTI j.
UNSPECV_BTI_JC ; Represent BTI jc.
UNSPECV_CHKFEAT ; Represent CHKFEAT X16.
+ UNSPECV_GCSPR ; Represent MRS Xn, GCSPR_EL0
+ UNSPECV_GCSPOPM ; Represent GCSPOPM.
+ UNSPECV_GCSSS1 ; Represent GCSSS1 Xt.
+ UNSPECV_GCSSS2 ; Represent GCSSS2 Xt.
UNSPECV_TSTART ; Represent transaction start.
UNSPECV_TCOMMIT ; Represent transaction commit.
UNSPECV_TCANCEL ; Represent transaction cancel.
@@ -8318,6 +8322,41 @@ (define_insn "aarch64_chkfeat"
"hint\\t40 // chkfeat x16"
)
+;; Guarded Control Stack (GCS) instructions
+(define_insn "aarch64_load_gcspr"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec_volatile:DI [(const_int 0)] UNSPECV_GCSPR))]
+ ""
+ "mrs\\t%0, s3_3_c2_c5_1 // gcspr_el0"
+ [(set_attr "type" "mrs")]
+)
+
+(define_insn "aarch64_gcspopm"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "0")]
UNSPECV_GCSPOPM))]
+ ""
+ "sysl\\t%0, #3, c7, c7, #1 // gcspopm"
+)
+
+(define_insn "aarch64_gcspopm_xzr"
+ [(unspec_volatile [(const_int 0)] UNSPECV_GCSPOPM)]
+ ""
+ "sysl\\txzr, #3, c7, c7, #1 // gcspopm"
+)
+
+(define_insn "aarch64_gcsss1"
+ [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
UNSPECV_GCSSS1)]
+ ""
+ "sys\\t#3, c7, c7, #2, %0 // gcsss1"
+)
+
+(define_insn "aarch64_gcsss2"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "0")]
UNSPECV_GCSSS2))]
+ ""
+ "sysl\\t%0, #3, c7, c7, #3 // gcsss2"
+)
+
;; AdvSIMD Stuff
(include "aarch64-simd.md")
--
2.39.5
