> From: Uros Bizjak <ubiz...@gmail.com>
> Sent: Friday, October 18, 2024 2:05 PM
>
> On Fri, Oct 18, 2024 at 4:56 AM Haochen Jiang <haochen.ji...@intel.com>
> wrote:
> >
> > Hi all,
> >
> > ISE054 has just been disclosed and you can find doc from here:
> >
> > https://cdrdv2.intel.com/v1/dl/getContent/671368
> >
> > From ISE, it shows that we will have family 0x13 for Diamond Rapids.
> > Therefore, we need to refactor the get_intel_cpu to accept new families.
> > Also I did some reorder in the switch for clearness by putting earlier
> > added products on top for search convenience.
>
> You can post "git diff -w" patch to see what the patch really does
> without drowning the real change in whitespace changes.
>
That is a good idea. The change after using git diff -w:
diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h
index 2ae383eb6ab..e3eb6e9d250 100644
--- a/gcc/common/config/i386/cpuinfo.h
+++ b/gcc/common/config/i386/cpuinfo.h
@@ -343,10 +343,8 @@ get_intel_cpu (struct __processor_model *cpu_model,
{
const char *cpu = NULL;
- /* Parse family and model only for model 6. */
- if (cpu_model2->__cpu_family != 0x6)
- return cpu;
-
+ /* Parse family and model for family 0x6. */
+ if (cpu_model2->__cpu_family == 0x6)
switch (cpu_model2->__cpu_model)
{
case 0x1c:
@@ -390,6 +388,15 @@ get_intel_cpu (struct __processor_model *cpu_model,
CHECK___builtin_cpu_is ("tremont");
cpu_model->__cpu_type = INTEL_TREMONT;
break;
+ case 0x17:
+ case 0x1d:
+ /* Penryn. */
+ case 0x0f:
+ /* Merom. */
+ cpu = "core2";
+ CHECK___builtin_cpu_is ("core2");
+ cpu_model->__cpu_type = INTEL_CORE2;
+ break;
case 0x1a:
case 0x1e:
case 0x1f:
@@ -466,14 +473,6 @@ get_intel_cpu (struct __processor_model *cpu_model,
cpu_model->__cpu_type = INTEL_COREI7;
cpu_model->__cpu_subtype = INTEL_COREI7_SKYLAKE;
break;
- case 0xa7:
- /* Rocket Lake. */
- cpu = "rocketlake";
- CHECK___builtin_cpu_is ("corei7");
- CHECK___builtin_cpu_is ("rocketlake");
- cpu_model->__cpu_type = INTEL_COREI7;
- cpu_model->__cpu_subtype = INTEL_COREI7_ROCKETLAKE;
- break;
case 0x55:
CHECK___builtin_cpu_is ("corei7");
cpu_model->__cpu_type = INTEL_COREI7;
@@ -509,6 +508,16 @@ get_intel_cpu (struct __processor_model *cpu_model,
cpu_model->__cpu_type = INTEL_COREI7;
cpu_model->__cpu_subtype = INTEL_COREI7_CANNONLAKE;
break;
+ case 0x7e:
+ case 0x7d:
+ case 0x9d:
+ /* Ice Lake client. */
+ cpu = "icelake-client";
+ CHECK___builtin_cpu_is ("corei7");
+ CHECK___builtin_cpu_is ("icelake-client");
+ cpu_model->__cpu_type = INTEL_COREI7;
+ cpu_model->__cpu_subtype = INTEL_COREI7_ICELAKE_CLIENT;
+ break;
case 0x6a:
case 0x6c:
/* Ice Lake server. */
@@ -518,15 +527,13 @@ get_intel_cpu (struct __processor_model *cpu_model,
cpu_model->__cpu_type = INTEL_COREI7;
cpu_model->__cpu_subtype = INTEL_COREI7_ICELAKE_SERVER;
break;
- case 0x7e:
- case 0x7d:
- case 0x9d:
- /* Ice Lake client. */
- cpu = "icelake-client";
+ case 0xa7:
+ /* Rocket Lake. */
+ cpu = "rocketlake";
CHECK___builtin_cpu_is ("corei7");
- CHECK___builtin_cpu_is ("icelake-client");
+ CHECK___builtin_cpu_is ("rocketlake");
cpu_model->__cpu_type = INTEL_COREI7;
- cpu_model->__cpu_subtype = INTEL_COREI7_ICELAKE_CLIENT;
+ cpu_model->__cpu_subtype = INTEL_COREI7_ROCKETLAKE;
break;
case 0x8c:
case 0x8d:
@@ -537,7 +544,6 @@ get_intel_cpu (struct __processor_model *cpu_model,
cpu_model->__cpu_type = INTEL_COREI7;
cpu_model->__cpu_subtype = INTEL_COREI7_TIGERLAKE;
break;
-
case 0xbe:
/* Alder Lake N, E-core only. */
case 0x97:
@@ -626,15 +632,6 @@ get_intel_cpu (struct __processor_model *cpu_model,
cpu_model->__cpu_type = INTEL_COREI7;
cpu_model->__cpu_subtype = INTEL_COREI7_PANTHERLAKE;
break;
- case 0x17:
- case 0x1d:
- /* Penryn. */
- case 0x0f:
- /* Merom. */
- cpu = "core2";
- CHECK___builtin_cpu_is ("core2");
- cpu_model->__cpu_type = INTEL_CORE2;
- break;
default:
break;
}
Thx,
Haochen
