On Fri, Oct 18, 2024 at 9:08 AM Antoni Boucher <boua...@zoho.com> wrote:
>
> Hi.
> This is a patch for the bug 116725.
> I'm not sure if it is a good fix, but it seems to do the job.
> If you have suggestions for better comments than what I wrote that would
> explain what's happening, I'm open to suggestions.

>@@ -7548,7 +7548,8 @@ (define_insn 
>"avx512fp16_vcvtph2<sseintconvertsignprefix><sseintconvert>_<mode><
>     [(match_operand:<ssePHmode> 1 "<round_nimm_predicate>" 
> "<round_constraint>")]
>     UNSPEC_US_FIX_NOTRUNC))]
>   "TARGET_AVX512FP16 && <round_mode_condition>"
>-  "vcvtph2<sseintconvertsignprefix><sseintconvert>\t{<round_mask_op2>%1, 
>%0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
>+;; %X1 so that we don't emit any *WORD PTR for -masm=intel.
>+  "vcvtph2<sseintconvertsignprefix><sseintconvert>\t{<round_mask_op2>%1, 
>%0<mask_operand2>|%0<mask_operand2>, %X1<round_mask_op2>}"
Could you define something like

 ;; Pointer size override for 16-bit upper-convert modes (Intel asm dialect)
 (define_mode_attr iptrh
  [(V32HI "") (V16SI "") (V8DI "")
   (V16HI "") (V8SI "") (V4DI "q")
   (V8HI "") (V4SI "q") (V2DI "k")])

And use
+  "vcvtph2<sseintconvertsignprefix><sseintconvert>\t{<round_mask_op2>%1,
%0<mask_operand2>|%0<mask_operand2>, %<iptrh>1<round_mask_op2>}"

>   [(set_attr "type" "ssecvt")
>    (set_attr "prefix" "evex")
>    (set_attr "mode" "<sseinsnmode>")])
>@@ -29854,7 +29855,8 @@ (define_insn 
>"avx512dq_vmfpclass<mode><mask_scalar_merge_name>"
>      UNSPEC_FPCLASS)
>    (const_int 1)))]
>    "TARGET_AVX512DQ || VALID_AVX512FP16_REG_MODE(<MODE>mode)"
>-   "vfpclass<ssescalarmodesuffix>\t{%2, %1, 
>%0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}";
>+;; %X1 so that we don't emit any *WORD PTR for -masm=intel.
>+   "vfpclass<ssescalarmodesuffix>\t{%2, %1, 
>%0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %X1, %2}";

For scaar memory operand rewrite, we usually use <iptr>, so
   "vfpclass<ssescalarmodesuffix>\t{%2, %1,
%0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>,
%<iptr>1, %2}";




-- 
BR,
Hongtao

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