On 04/09/2024 14:26, Christophe Lyon wrote: > Factorize vcvtaq vcvtmq vcvtnq vcvtpq builtins so that they use the > same parameterized names. > > 2024-07-11 Christophe Lyon <christophe.l...@linaro.org> > > gcc/ > * config/arm/iterators.md (mve_insn): Add VCVTAQ_M_S, VCVTAQ_M_U, > VCVTAQ_S, VCVTAQ_U, VCVTMQ_M_S, VCVTMQ_M_U, VCVTMQ_S, VCVTMQ_U, > VCVTNQ_M_S, VCVTNQ_M_U, VCVTNQ_S, VCVTNQ_U, VCVTPQ_M_S, > VCVTPQ_M_U, VCVTPQ_S, VCVTPQ_U. > (VCVTAQ, VCVTPQ, VCVTNQ, VCVTMQ, VCVTAQ_M, VCVTMQ_M, VCVTNQ_M) > (VCVTPQ_M): Delete. > (VCVTxQ, VCVTxQ_M): New. > * config/arm/mve.md (mve_vcvtpq_<supf><mode>) > (mve_vcvtnq_<supf><mode>, mve_vcvtmq_<supf><mode>) > (mve_vcvtaq_<supf><mode>): Merge into ... > (@mve_<mve_insn>q_<supf><mode>): ... this. > (mve_vcvtaq_m_<supf><mode>, mve_vcvtmq_m_<supf><mode>) > (mve_vcvtpq_m_<supf><mode>, mve_vcvtnq_m_<supf><mode>): Merge into > ... > (@mve_<mve_insn>q_m_<supf><mode>): ... this.
OK R. > --- > gcc/config/arm/iterators.md | 18 +++--- > gcc/config/arm/mve.md | 121 +++++------------------------------- > 2 files changed, 26 insertions(+), 113 deletions(-) > > diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md > index b9c39a98ca2..162c0d56bfb 100644 > --- a/gcc/config/arm/iterators.md > +++ b/gcc/config/arm/iterators.md > @@ -964,10 +964,18 @@ (define_int_attr mve_insn [ > (VCMLAQ_M_F "vcmla") (VCMLAQ_ROT90_M_F "vcmla") > (VCMLAQ_ROT180_M_F "vcmla") (VCMLAQ_ROT270_M_F "vcmla") > (VCMULQ_M_F "vcmul") (VCMULQ_ROT90_M_F "vcmul") > (VCMULQ_ROT180_M_F "vcmul") (VCMULQ_ROT270_M_F "vcmul") > (VCREATEQ_S "vcreate") (VCREATEQ_U "vcreate") (VCREATEQ_F > "vcreate") > + (VCVTAQ_M_S "vcvta") (VCVTAQ_M_U "vcvta") > + (VCVTAQ_S "vcvta") (VCVTAQ_U "vcvta") > (VCVTBQ_F16_F32 "vcvtb") (VCVTTQ_F16_F32 "vcvtt") > (VCVTBQ_F32_F16 "vcvtb") (VCVTTQ_F32_F16 "vcvtt") > (VCVTBQ_M_F16_F32 "vcvtb") (VCVTTQ_M_F16_F32 "vcvtt") > (VCVTBQ_M_F32_F16 "vcvtb") (VCVTTQ_M_F32_F16 "vcvtt") > + (VCVTMQ_M_S "vcvtm") (VCVTMQ_M_U "vcvtm") > + (VCVTMQ_S "vcvtm") (VCVTMQ_U "vcvtm") > + (VCVTNQ_M_S "vcvtn") (VCVTNQ_M_U "vcvtn") > + (VCVTNQ_S "vcvtn") (VCVTNQ_U "vcvtn") > + (VCVTPQ_M_S "vcvtp") (VCVTPQ_M_U "vcvtp") > + (VCVTPQ_S "vcvtp") (VCVTPQ_U "vcvtp") > (VCVTQ_FROM_F_S "vcvt") (VCVTQ_FROM_F_U "vcvt") > (VCVTQ_M_FROM_F_S "vcvt") (VCVTQ_M_FROM_F_U "vcvt") > (VCVTQ_M_N_FROM_F_S "vcvt") (VCVTQ_M_N_FROM_F_U "vcvt") > @@ -2732,14 +2740,10 @@ (define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S]) > (define_int_iterator VREV64Q [VREV64Q_S VREV64Q_U]) > (define_int_iterator VCVTQ_FROM_F [VCVTQ_FROM_F_S VCVTQ_FROM_F_U]) > (define_int_iterator VREV16Q [VREV16Q_U VREV16Q_S]) > -(define_int_iterator VCVTAQ [VCVTAQ_U VCVTAQ_S]) > (define_int_iterator VDUPQ_N [VDUPQ_N_U VDUPQ_N_S]) > (define_int_iterator VADDVQ [VADDVQ_U VADDVQ_S]) > (define_int_iterator VREV32Q [VREV32Q_U VREV32Q_S]) > (define_int_iterator VMOVLxQ [VMOVLBQ_S VMOVLBQ_U VMOVLTQ_U VMOVLTQ_S]) > -(define_int_iterator VCVTPQ [VCVTPQ_S VCVTPQ_U]) > -(define_int_iterator VCVTNQ [VCVTNQ_S VCVTNQ_U]) > -(define_int_iterator VCVTMQ [VCVTMQ_S VCVTMQ_U]) > (define_int_iterator VADDLVQ [VADDLVQ_U VADDLVQ_S]) > (define_int_iterator VCVTQ_N_TO_F [VCVTQ_N_TO_F_S VCVTQ_N_TO_F_U]) > (define_int_iterator VCREATEQ [VCREATEQ_U VCREATEQ_S]) > @@ -2795,7 +2799,6 @@ (define_int_iterator VQMOVNTQ [VQMOVNTQ_U VQMOVNTQ_S]) > (define_int_iterator VSHLLxQ_N [VSHLLBQ_N_S VSHLLBQ_N_U VSHLLTQ_N_S > VSHLLTQ_N_U]) > (define_int_iterator VRMLALDAVHQ [VRMLALDAVHQ_U VRMLALDAVHQ_S]) > (define_int_iterator VBICQ_M_N [VBICQ_M_N_S VBICQ_M_N_U]) > -(define_int_iterator VCVTAQ_M [VCVTAQ_M_S VCVTAQ_M_U]) > (define_int_iterator VCVTQ_M_TO_F [VCVTQ_M_TO_F_S VCVTQ_M_TO_F_U]) > (define_int_iterator VQRSHRNBQ_N [VQRSHRNBQ_N_U VQRSHRNBQ_N_S]) > (define_int_iterator VABAVQ [VABAVQ_S VABAVQ_U]) > @@ -2845,9 +2848,6 @@ (define_int_iterator VQMOVNTQ_M [VQMOVNTQ_M_U > VQMOVNTQ_M_S]) > (define_int_iterator VMVNQ_M_N [VMVNQ_M_N_U VMVNQ_M_N_S]) > (define_int_iterator VQSHRNTQ_N [VQSHRNTQ_N_U VQSHRNTQ_N_S]) > (define_int_iterator VSHRNTQ_N [VSHRNTQ_N_S VSHRNTQ_N_U]) > -(define_int_iterator VCVTMQ_M [VCVTMQ_M_S VCVTMQ_M_U]) > -(define_int_iterator VCVTNQ_M [VCVTNQ_M_S VCVTNQ_M_U]) > -(define_int_iterator VCVTPQ_M [VCVTPQ_M_S VCVTPQ_M_U]) > (define_int_iterator VCVTQ_M_N_FROM_F [VCVTQ_M_N_FROM_F_S > VCVTQ_M_N_FROM_F_U]) > (define_int_iterator VCVTQ_M_FROM_F [VCVTQ_M_FROM_F_U VCVTQ_M_FROM_F_S]) > (define_int_iterator VRMLALDAVHQ_P [VRMLALDAVHQ_P_S VRMLALDAVHQ_P_U]) > @@ -2956,6 +2956,8 @@ (define_int_iterator VCVTxQ_F16_F32 [VCVTBQ_F16_F32 > VCVTTQ_F16_F32]) > (define_int_iterator VCVTxQ_F32_F16 [VCVTBQ_F32_F16 VCVTTQ_F32_F16]) > (define_int_iterator VCVTxQ_M_F16_F32 [VCVTBQ_M_F16_F32 VCVTTQ_M_F16_F32]) > (define_int_iterator VCVTxQ_M_F32_F16 [VCVTBQ_M_F32_F16 VCVTTQ_M_F32_F16]) > +(define_int_iterator VCVTxQ [VCVTAQ_S VCVTAQ_U VCVTMQ_S VCVTMQ_U VCVTNQ_S > VCVTNQ_U VCVTPQ_S VCVTPQ_U]) > +(define_int_iterator VCVTxQ_M [VCVTAQ_M_S VCVTAQ_M_U VCVTMQ_M_S VCVTMQ_M_U > VCVTNQ_M_S VCVTNQ_M_U VCVTPQ_M_S VCVTPQ_M_U]) > (define_int_iterator DLSTP [DLSTP8 DLSTP16 DLSTP32 > DLSTP64]) > (define_int_iterator LETP [LETP8 LETP16 LETP32 > diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md > index 6e2f542cdae..41c7e73a161 100644 > --- a/gcc/config/arm/mve.md > +++ b/gcc/config/arm/mve.md > @@ -416,62 +416,20 @@ (define_insn "@mve_<mve_insn>q_<supf><mode>" > ]) > > ;; > -;; [vcvtpq_s, vcvtpq_u]) > +;; [vcvtaq_u, vcvtaq_s] > +;; [vcvtmq_s, vcvtmq_u] > +;; [vcvtnq_s, vcvtnq_u] > +;; [vcvtpq_s, vcvtpq_u] > ;; > -(define_insn "mve_vcvtpq_<supf><mode>" > - [ > - (set (match_operand:MVE_5 0 "s_register_operand" "=w") > - (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")] > - VCVTPQ)) > - ] > - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > - "vcvtp.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1" > - [(set (attr "mve_unpredicated_insn") (symbol_ref > "CODE_FOR_mve_vcvtpq_<supf><mode>")) > - (set_attr "type" "mve_move") > -]) > - > -;; > -;; [vcvtnq_s, vcvtnq_u]) > -;; > -(define_insn "mve_vcvtnq_<supf><mode>" > - [ > - (set (match_operand:MVE_5 0 "s_register_operand" "=w") > - (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")] > - VCVTNQ)) > - ] > - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > - "vcvtn.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1" > - [(set (attr "mve_unpredicated_insn") (symbol_ref > "CODE_FOR_mve_vcvtnq_<supf><mode>")) > - (set_attr "type" "mve_move") > -]) > - > -;; > -;; [vcvtmq_s, vcvtmq_u]) > -;; > -(define_insn "mve_vcvtmq_<supf><mode>" > - [ > - (set (match_operand:MVE_5 0 "s_register_operand" "=w") > - (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")] > - VCVTMQ)) > - ] > - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > - "vcvtm.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1" > - [(set (attr "mve_unpredicated_insn") (symbol_ref > "CODE_FOR_mve_vcvtmq_<supf><mode>")) > - (set_attr "type" "mve_move") > -]) > - > -;; > -;; [vcvtaq_u, vcvtaq_s]) > -;; > -(define_insn "mve_vcvtaq_<supf><mode>" > +(define_insn "@mve_<mve_insn>q_<supf><mode>" > [ > (set (match_operand:MVE_5 0 "s_register_operand" "=w") > (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")] > - VCVTAQ)) > + VCVTxQ)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > - "vcvta.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1" > - [(set (attr "mve_unpredicated_insn") (symbol_ref > "CODE_FOR_mve_vcvtaq_<supf><mode>")) > + "<mve_insn>.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1" > + [(set (attr "mve_unpredicated_insn") (symbol_ref > "CODE_FOR_mve_<mve_insn>q_<supf><mode>")) > (set_attr "type" "mve_move") > ]) > > @@ -1627,19 +1585,22 @@ (define_insn "@mve_vcmp<mve_cmp_op1>q_m_f<mode>" > (set_attr "length""8")]) > > ;; > -;; [vcvtaq_m_u, vcvtaq_m_s]) > +;; [vcvtaq_m_u, vcvtaq_m_s] > +;; [vcvtmq_m_s, vcvtmq_m_u] > +;; [vcvtnq_m_s, vcvtnq_m_u] > +;; [vcvtpq_m_u, vcvtpq_m_s] > ;; > -(define_insn "mve_vcvtaq_m_<supf><mode>" > +(define_insn "@mve_<mve_insn>q_m_<supf><mode>" > [ > (set (match_operand:MVE_5 0 "s_register_operand" "=w") > (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") > (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") > (match_operand:<MVE_VPRED> 3 "vpr_register_operand" > "Up")] > - VCVTAQ_M)) > + VCVTxQ_M)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > - "vpst\;vcvtat.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2" > - [(set (attr "mve_unpredicated_insn") (symbol_ref > "CODE_FOR_mve_vcvtaq_<supf><mode>")) > + "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2" > + [(set (attr "mve_unpredicated_insn") (symbol_ref > "CODE_FOR_mve_<mve_insn>q_<supf><mode>")) > (set_attr "type" "mve_move") > (set_attr "length""8")]) > > @@ -2539,56 +2500,6 @@ (define_insn "@mve_<mve_insn>q_p_<supf>v4si" > (set_attr "type" "mve_move") > (set_attr "length""8")]) > > -;; > -;; [vcvtmq_m_s, vcvtmq_m_u]) > -;; > -(define_insn "mve_vcvtmq_m_<supf><mode>" > - [ > - (set (match_operand:MVE_5 0 "s_register_operand" "=w") > - (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") > - (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") > - (match_operand:<MVE_VPRED> 3 "vpr_register_operand" > "Up")] > - VCVTMQ_M)) > - ] > - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > - "vpst\;vcvtmt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2" > - [(set (attr "mve_unpredicated_insn") (symbol_ref > "CODE_FOR_mve_vcvtmq_<supf><mode>")) > - (set_attr "type" "mve_move") > - (set_attr "length""8")]) > - > -;; > -;; [vcvtpq_m_u, vcvtpq_m_s]) > -;; > -(define_insn "mve_vcvtpq_m_<supf><mode>" > - [ > - (set (match_operand:MVE_5 0 "s_register_operand" "=w") > - (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") > - (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") > - (match_operand:<MVE_VPRED> 3 "vpr_register_operand" > "Up")] > - VCVTPQ_M)) > - ] > - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > - "vpst\;vcvtpt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2" > - [(set (attr "mve_unpredicated_insn") (symbol_ref > "CODE_FOR_mve_vcvtpq_<supf><mode>")) > - (set_attr "type" "mve_move") > - (set_attr "length""8")]) > - > -;; > -;; [vcvtnq_m_s, vcvtnq_m_u]) > -;; > -(define_insn "mve_vcvtnq_m_<supf><mode>" > - [ > - (set (match_operand:MVE_5 0 "s_register_operand" "=w") > - (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") > - (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") > - (match_operand:<MVE_VPRED> 3 "vpr_register_operand" > "Up")] > - VCVTNQ_M)) > - ] > - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > - "vpst\;vcvtnt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2" > - [(set (attr "mve_unpredicated_insn") (symbol_ref > "CODE_FOR_mve_vcvtnq_<supf><mode>")) > - (set_attr "type" "mve_move") > - (set_attr "length""8")]) > > ;; > ;; [vcvtq_m_n_from_f_s, vcvtq_m_n_from_f_u]
