From: Pan Li <pan2...@intel.com>
Form 3:
#define DEF_VEC_SAT_S_TRUNC_FMT_3(NT, WT, NT_MIN, NT_MAX) \
void __attribute__((noinline)) \
vec_sat_s_trunc_##NT##_##WT##_fmt_3 (NT *out, WT *in, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
WT x = in[i]; \
NT trunc = (NT)x; \
out[i] = (WT)NT_MIN < x && x < (WT)NT_MAX \
? trunc \
: x < 0 ? NT_MIN : NT_MAX; \
} \
}
The below test are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper macros.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i16-to-i8.c: New
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i32-to-i16.c: New
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i32-to-i8.c: New
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i16.c: New
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i32.c: New
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i8.c: New
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i16-to-i8.c:
New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i32-to-i16.c:
New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i32-to-i8.c:
New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i16.c:
New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i32.c:
New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i8.c:
New test.
Signed-off-by: Pan Li <pan2...@intel.com>
---
.../unop/vec_sat_s_trunc-3-i16-to-i8.c | 9 ++++++++
.../unop/vec_sat_s_trunc-3-i32-to-i16.c | 9 ++++++++
.../unop/vec_sat_s_trunc-3-i32-to-i8.c | 9 ++++++++
.../unop/vec_sat_s_trunc-3-i64-to-i16.c | 9 ++++++++
.../unop/vec_sat_s_trunc-3-i64-to-i32.c | 9 ++++++++
.../unop/vec_sat_s_trunc-3-i64-to-i8.c | 9 ++++++++
.../unop/vec_sat_s_trunc-run-3-i16-to-i8.c | 16 ++++++++++++++
.../unop/vec_sat_s_trunc-run-3-i32-to-i16.c | 16 ++++++++++++++
.../unop/vec_sat_s_trunc-run-3-i32-to-i8.c | 16 ++++++++++++++
.../unop/vec_sat_s_trunc-run-3-i64-to-i16.c | 16 ++++++++++++++
.../unop/vec_sat_s_trunc-run-3-i64-to-i32.c | 16 ++++++++++++++
.../unop/vec_sat_s_trunc-run-3-i64-to-i8.c | 16 ++++++++++++++
.../riscv/rvv/autovec/vec_sat_arith.h | 22 +++++++++++++++++++
13 files changed, 172 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i16-to-i8.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i32-to-i16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i32-to-i8.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i8.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i16-to-i8.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i32-to-i16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i32-to-i8.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i8.c
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i16-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i16-to-i8.c
new file mode 100644
index 00000000000..392366def06
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i16-to-i8.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_TRUNC_FMT_3(int8_t, int16_t, INT8_MIN, INT8_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i32-to-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i32-to-i16.c
new file mode 100644
index 00000000000..2b16049994a
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i32-to-i16.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_TRUNC_FMT_3(int16_t, int32_t, INT16_MIN, INT16_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i32-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i32-to-i8.c
new file mode 100644
index 00000000000..b444d2ea9c6
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i32-to-i8.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_TRUNC_FMT_3(int8_t, int32_t, INT8_MIN, INT8_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i16.c
new file mode 100644
index 00000000000..06606581e8f
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i16.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_TRUNC_FMT_3(int16_t, int64_t, INT16_MIN, INT16_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i32.c
new file mode 100644
index 00000000000..72ec727274b
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i32.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_TRUNC_FMT_3(int32_t, int64_t, INT32_MIN, INT32_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i8.c
new file mode 100644
index 00000000000..7915d5417a5
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i8.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_TRUNC_FMT_3(int8_t, int64_t, INT8_MIN, INT8_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i16-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i16-to-i8.c
new file mode 100644
index 00000000000..0b658f3d0aa
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i16-to-i8.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T1 int8_t
+#define T2 int16_t
+
+DEF_VEC_SAT_S_TRUNC_FMT_3_WRAP(T1, T2, INT8_MIN, INT8_MAX)
+
+#define T TEST_UNARY_STRUCT_DECL(T1, T2)
+#define DATA TEST_UNARY_DATA_WRAP(T1, T2)
+#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_3_WRAP(T1, T2, out, in,
N)
+
+#include "vec_sat_unary_vv_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i32-to-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i32-to-i16.c
new file mode 100644
index 00000000000..41e1789dd62
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i32-to-i16.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T1 int16_t
+#define T2 int32_t
+
+DEF_VEC_SAT_S_TRUNC_FMT_3_WRAP(T1, T2, INT16_MIN, INT16_MAX)
+
+#define T TEST_UNARY_STRUCT_DECL(T1, T2)
+#define DATA TEST_UNARY_DATA_WRAP(T1, T2)
+#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_3_WRAP(T1, T2, out, in,
N)
+
+#include "vec_sat_unary_vv_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i32-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i32-to-i8.c
new file mode 100644
index 00000000000..0b658f3d0aa
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i32-to-i8.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T1 int8_t
+#define T2 int16_t
+
+DEF_VEC_SAT_S_TRUNC_FMT_3_WRAP(T1, T2, INT8_MIN, INT8_MAX)
+
+#define T TEST_UNARY_STRUCT_DECL(T1, T2)
+#define DATA TEST_UNARY_DATA_WRAP(T1, T2)
+#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_3_WRAP(T1, T2, out, in,
N)
+
+#include "vec_sat_unary_vv_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i16.c
new file mode 100644
index 00000000000..28cd5c806f9
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i16.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T1 int16_t
+#define T2 int64_t
+
+DEF_VEC_SAT_S_TRUNC_FMT_3_WRAP(T1, T2, INT16_MIN, INT16_MAX)
+
+#define T TEST_UNARY_STRUCT_DECL(T1, T2)
+#define DATA TEST_UNARY_DATA_WRAP(T1, T2)
+#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_3_WRAP(T1, T2, out, in,
N)
+
+#include "vec_sat_unary_vv_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i32.c
new file mode 100644
index 00000000000..a6501f93df7
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i32.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T1 int32_t
+#define T2 int64_t
+
+DEF_VEC_SAT_S_TRUNC_FMT_3_WRAP(T1, T2, INT32_MIN, INT32_MAX)
+
+#define T TEST_UNARY_STRUCT_DECL(T1, T2)
+#define DATA TEST_UNARY_DATA_WRAP(T1, T2)
+#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_3_WRAP(T1, T2, out, in,
N)
+
+#include "vec_sat_unary_vv_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i8.c
new file mode 100644
index 00000000000..eef36e8dbdb
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i8.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T1 int8_t
+#define T2 int64_t
+
+DEF_VEC_SAT_S_TRUNC_FMT_3_WRAP(T1, T2, INT8_MIN, INT8_MAX)
+
+#define T TEST_UNARY_STRUCT_DECL(T1, T2)
+#define DATA TEST_UNARY_DATA_WRAP(T1, T2)
+#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_3_WRAP(T1, T2, out, in,
N)
+
+#include "vec_sat_unary_vv_run.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h
index 5c8436f7e28..c0524bae2d0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h
@@ -681,6 +681,23 @@ vec_sat_s_trunc_##NT##_##WT##_fmt_2 (NT *out, WT *in,
unsigned limit) \
#define DEF_VEC_SAT_S_TRUNC_FMT_2_WRAP(NT, WT, NT_MIN, NT_MAX) \
DEF_VEC_SAT_S_TRUNC_FMT_2(NT, WT, NT_MIN, NT_MAX)
+#define DEF_VEC_SAT_S_TRUNC_FMT_3(NT, WT, NT_MIN, NT_MAX) \
+void __attribute__((noinline)) \
+vec_sat_s_trunc_##NT##_##WT##_fmt_3 (NT *out, WT *in, unsigned limit) \
+{ \
+ unsigned i; \
+ for (i = 0; i < limit; i++) \
+ { \
+ WT x = in[i]; \
+ NT trunc = (NT)x; \
+ out[i] = (WT)NT_MIN < x && x <= (WT)NT_MAX \
+ ? trunc \
+ : x < 0 ? NT_MIN : NT_MAX; \
+ } \
+}
+#define DEF_VEC_SAT_S_TRUNC_FMT_3_WRAP(NT, WT, NT_MIN, NT_MAX) \
+ DEF_VEC_SAT_S_TRUNC_FMT_3(NT, WT, NT_MIN, NT_MAX)
+
#define RUN_VEC_SAT_U_TRUNC_FMT_1(NT, WT, out, in, N) \
vec_sat_u_trunc_##NT##_##WT##_fmt_1 (out, in, N)
#define RUN_VEC_SAT_U_TRUNC_FMT_1_WRAP(NT, WT, out, in, N) \
@@ -711,4 +728,9 @@ vec_sat_s_trunc_##NT##_##WT##_fmt_2 (NT *out, WT *in,
unsigned limit) \
#define RUN_VEC_SAT_S_TRUNC_FMT_2_WRAP(NT, WT, out, in, N) \
RUN_VEC_SAT_S_TRUNC_FMT_2(NT, WT, out, in, N)
+#define RUN_VEC_SAT_S_TRUNC_FMT_3(NT, WT, out, in, N) \
+ vec_sat_s_trunc_##NT##_##WT##_fmt_3 (out, in, N)
+#define RUN_VEC_SAT_S_TRUNC_FMT_3_WRAP(NT, WT, out, in, N) \
+ RUN_VEC_SAT_S_TRUNC_FMT_3(NT, WT, out, in, N)
+
#endif
--
2.43.0
