Andrew Carlotti <andrew.carlo...@arm.com> writes:
> This includes +fcma as a dependency of +sve, and means that we can
> finally support fcma intrinsics on a64fx.
>
> Also add fcma to the Features list in several cpunative testcases that
> incorrectly included sve without fcma.
>
> gcc/ChangeLog:
>
> * config/aarch64/aarch64-arches.def (V8_3A): Add FCMA.
> * config/aarch64/aarch64-option-extensions.def (FCMA): New flag.
> (SVE): Add FCMA dependency.
> * config/aarch64/aarch64.h (TARGET_COMPLEX): Use new flag.
> * config/aarch64/arm_neon.h: Use new flag for fcma intrinsics.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/aarch64/cpunative/info_15: Add fcma to Features.
> * gcc.target/aarch64/cpunative/info_16: Ditto.
> * gcc.target/aarch64/cpunative/info_17: Ditto.
> * gcc.target/aarch64/cpunative/info_8: Ditto.
> * gcc.target/aarch64/cpunative/info_9: Ditto.
In addition to Andrew P's comment about documentation, doesn't this
mean that -mcpu=native will now emit +fcma .arch strings for
unrecognised CPUs (i.e. those for which we can't establish a
baseline beyond Armv8-A?). E.g., I think:
processor : 0
BogoMIPS : 100.00
Features : fp asimd atomics crc32 asimdrdm paca pacg lrcpc fcma
CPU implementer : 0xaa
CPU architecture: 8
CPU variant : 0xaa
CPU part : 0xaa
CPU revision : 0
should enable all the Armv8.3-A features that GCC is aware of after
this patch, but we emit:
.arch armv8-a+lse+rdma+crc+fcma+rcpc+pauth
rather than:
.arch armv8.3-a
And that could be a problem because binutils support for the +fcma
name is relatively recent (your patch from January this year).
Assembling with older versions of gas is likely to fail, regardless
of whether the code uses FCMA.
I think we might need to adjust the driver code so that it tries
to consolidate features into an architecture level where possible.
That does theoretically run the risk of making gas enable features that
GCC isn't aware of and that aren't available on the CPU (for cases where
Armv8.X-A+features looks like Armv8.Y-A to GCC, but isn't because of a
missing feature that GCC doesn't know about). The current code gets
that wrong in the opposite direction, though, as the above example
shows: we wouldn't enable FCMA support even if the target has it.
I think it's ok for odd combinations like -march=armv8.3-a+nofcma
to reference fcma in the .arch string. But for compatibility,
I think we need to avoid adding it to .arch strings for command lines
that previously worked with older binutils.
Thanks,
Richard
> diff --git a/gcc/config/aarch64/aarch64-arches.def
> b/gcc/config/aarch64/aarch64-arches.def
> index
> 4634b272e28006b5c6c2d6705a2f1010cbd9ab9b..fadf9c36b03865a3af9b25888a50f5bf3abe37b7
> 100644
> --- a/gcc/config/aarch64/aarch64-arches.def
> +++ b/gcc/config/aarch64/aarch64-arches.def
> @@ -33,7 +33,7 @@
> AARCH64_ARCH("armv8-a", generic_armv8_a, V8A, 8, (SIMD))
> AARCH64_ARCH("armv8.1-a", generic_armv8_a, V8_1A, 8, (V8A, LSE,
> CRC, RDMA))
> AARCH64_ARCH("armv8.2-a", generic_armv8_a, V8_2A, 8, (V8_1A))
> -AARCH64_ARCH("armv8.3-a", generic_armv8_a, V8_3A, 8, (V8_2A,
> PAUTH, RCPC))
> +AARCH64_ARCH("armv8.3-a", generic_armv8_a, V8_3A, 8, (V8_2A,
> PAUTH, RCPC, FCMA))
> AARCH64_ARCH("armv8.4-a", generic_armv8_a, V8_4A, 8, (V8_3A,
> F16FML, DOTPROD, FLAGM))
> AARCH64_ARCH("armv8.5-a", generic_armv8_a, V8_5A, 8, (V8_4A, SB,
> SSBS, PREDRES))
> AARCH64_ARCH("armv8.6-a", generic_armv8_a, V8_6A, 8, (V8_5A,
> I8MM, BF16))
> diff --git a/gcc/config/aarch64/aarch64-option-extensions.def
> b/gcc/config/aarch64/aarch64-option-extensions.def
> index
> 8279f5a76eae7d787b8126044c5b4b4b78e97324..12640ed970d0475b9e28f1c4f1c6295e88e1ab97
> 100644
> --- a/gcc/config/aarch64/aarch64-option-extensions.def
> +++ b/gcc/config/aarch64/aarch64-option-extensions.def
> @@ -151,6 +151,8 @@ AARCH64_OPT_EXTENSION("fp16fml", F16FML, (), (F16), (),
> "asimdfhm")
>
> AARCH64_FMV_FEATURE("fp16fml", FP16FML, (F16FML))
>
> +AARCH64_OPT_FMV_EXTENSION("fcma", FCMA, (SIMD), (), (), "fcma")
> +
> AARCH64_OPT_FMV_EXTENSION("rcpc", RCPC, (), (), (), "lrcpc")
>
> AARCH64_OPT_FMV_EXTENSION("rcpc3", RCPC3, (RCPC), (), (), "lrcpc3")
> @@ -163,7 +165,7 @@ AARCH64_OPT_FMV_EXTENSION("bf16", BF16, (FP), (SIMD), (),
> "bf16")
>
> AARCH64_FMV_FEATURE("rpres", RPRES, ())
>
> -AARCH64_OPT_FMV_EXTENSION("sve", SVE, (SIMD, F16), (), (), "sve")
> +AARCH64_OPT_FMV_EXTENSION("sve", SVE, (SIMD, F16, FCMA), (), (), "sve")
>
> AARCH64_OPT_EXTENSION("f32mm", F32MM, (SVE), (), (), "f32mm")
>
> diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
> index
> 030cffb17606c1062af62398dd631bae50b448af..0c3d7baf7c85e54f7dd63fedb2da80d654c9ea50
> 100644
> --- a/gcc/config/aarch64/aarch64.h
> +++ b/gcc/config/aarch64/aarch64.h
> @@ -364,7 +364,7 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE
> ATTRIBUTE_UNUSED
> #define TARGET_JSCVT (TARGET_FLOAT && TARGET_ARMV8_3)
>
> /* Armv8.3-a Complex number extension to AdvSIMD extensions. */
> -#define TARGET_COMPLEX (TARGET_SIMD && TARGET_ARMV8_3)
> +#define TARGET_COMPLEX AARCH64_HAVE_ISA (FCMA)
>
> /* Floating-point rounding instructions from Armv8.5-a. */
> #define TARGET_FRINT (AARCH64_HAVE_ISA (V8_5A) && TARGET_FLOAT)
> diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
> index
> e376685489da055029def6b661132b5154886b57..0ab511a884126821ecae7d2fc7c1a3427bdfe5ac
> 100644
> --- a/gcc/config/aarch64/arm_neon.h
> +++ b/gcc/config/aarch64/arm_neon.h
> @@ -27015,7 +27015,7 @@ vbcaxq_s64 (int64x2_t __a, int64x2_t __b, int64x2_t
> __c)
> /* AdvSIMD Complex numbers intrinsics. */
>
> #pragma GCC push_options
> -#pragma GCC target ("arch=armv8.3-a")
> +#pragma GCC target ("+nothing+fcma")
>
> #pragma GCC push_options
> #pragma GCC target ("+fp16")
> diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_15
> b/gcc/testsuite/gcc.target/aarch64/cpunative/info_15
> index
> 6b425ea201351247c7273718d9e1e52cae62b342..1a31a75d6b4842846ad6d9476df23aae5ef72f83
> 100644
> --- a/gcc/testsuite/gcc.target/aarch64/cpunative/info_15
> +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_15
> @@ -1,6 +1,6 @@
> processor : 0
> BogoMIPS : 100.00
> -Features : Lorem ipsum dolor sit ametd rebum expetendis per at Dolor
> lucilius referrentur ei mei virtute eruditi eum ne Iisque verter svesm4 asimd
> fp sve sve2 fphp asimdhp sm3 sm4
> +Features : Lorem ipsum dolor sit ametd rebum expetendis per at Dolor
> lucilius referrentur ei mei virtute eruditi eum ne Iisque verter svesm4 asimd
> fp sve sve2 fphp asimdhp sm3 sm4 fcma
> CPU implementer : 0x41
> CPU architecture: 8
> CPU variant : 0x0
> diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_16
> b/gcc/testsuite/gcc.target/aarch64/cpunative/info_16
> index
> 26f01c4962489ab116450dd55717e4db345fdaee..cdff314be73842b434fe39ecaf5bddbb778320ce
> 100644
> --- a/gcc/testsuite/gcc.target/aarch64/cpunative/info_16
> +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_16
> @@ -1,6 +1,6 @@
> processor : 0
> BogoMIPS : 100.00
> -Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 asimddp sve sve2
> fphp asimdhp
> +Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 asimddp sve sve2
> fphp asimdhp fcma
> CPU implementer : 0xfe
> CPU architecture: 8
> CPU variant : 0x0
> diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_17
> b/gcc/testsuite/gcc.target/aarch64/cpunative/info_17
> index
> 26f01c4962489ab116450dd55717e4db345fdaee..cdff314be73842b434fe39ecaf5bddbb778320ce
> 100644
> --- a/gcc/testsuite/gcc.target/aarch64/cpunative/info_17
> +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_17
> @@ -1,6 +1,6 @@
> processor : 0
> BogoMIPS : 100.00
> -Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 asimddp sve sve2
> fphp asimdhp
> +Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 asimddp sve sve2
> fphp asimdhp fcma
> CPU implementer : 0xfe
> CPU architecture: 8
> CPU variant : 0x0
> diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_8
> b/gcc/testsuite/gcc.target/aarch64/cpunative/info_8
> index
> 76da16c57b545c0cf72bf96e8a56f502ecc55073..37a488946b16c5fd05434a36d58b0af4d7221c04
> 100644
> --- a/gcc/testsuite/gcc.target/aarch64/cpunative/info_8
> +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_8
> @@ -1,6 +1,6 @@
> processor : 0
> BogoMIPS : 100.00
> -Features : asimd sve fp fphp asimdhp
> +Features : asimd sve fp fphp asimdhp fcma
> CPU implementer : 0x41
> CPU architecture: 8
> CPU variant : 0x0
> diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_9
> b/gcc/testsuite/gcc.target/aarch64/cpunative/info_9
> index
> 14703dd1d0bf0c6543484d34950dc91778483b67..171ba498feabbb5ea2d392bc8ad0b11f156895ed
> 100644
> --- a/gcc/testsuite/gcc.target/aarch64/cpunative/info_9
> +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_9
> @@ -1,6 +1,6 @@
> processor : 0
> BogoMIPS : 100.00
> -Features : asimd fp svesm4 sve sve2 fphp asimdhp sm3 sm4
> +Features : asimd fp svesm4 sve sve2 fphp asimdhp sm3 sm4 fcma
> CPU implementer : 0x41
> CPU architecture: 8
> CPU variant : 0x0
