From: Pan Li <pan2...@intel.com>
This patch would like to implement the sssub form 1. Aka:
Form 1:
#define DEF_SAT_S_SUB_FMT_1(T, UT, MIN, MAX) \
T __attribute__((noinline)) \
sat_s_sub_##T##_fmt_1 (T x, T y) \
{ \
T minus = (UT)x - (UT)y; \
return (x ^ y) >= 0 \
? minus \
: (minus ^ x) >= 0 \
? minus \
: x < 0 ? MIN : MAX; \
}
DEF_SAT_S_SUB_FMT_1(int8_t, uint8_t, INT8_MIN, INT8_MAX)
Before this patch:
10 │ sat_s_sub_int8_t_fmt_1:
11 │ subw a5,a0,a1
12 │ slliw a5,a5,24
13 │ sraiw a5,a5,24
14 │ xor a1,a0,a1
15 │ xor a4,a0,a5
16 │ and a1,a1,a4
17 │ blt a1,zero,.L4
18 │ mv a0,a5
19 │ ret
20 │ .L4:
21 │ srai a0,a0,63
22 │ xori a5,a0,127
23 │ mv a0,a5
24 │ ret
After this patch:
10 │ sat_s_sub_int8_t_fmt_1:
11 │ sub a4,a0,a1
12 │ xor a5,a0,a4
13 │ xor a1,a0,a1
14 │ and a5,a5,a1
15 │ srli a5,a5,7
16 │ andi a5,a5,1
17 │ srai a0,a0,63
18 │ xori a3,a0,127
19 │ neg a0,a5
20 │ addi a5,a5,-1
21 │ and a3,a3,a0
22 │ and a0,a4,a5
23 │ or a0,a0,a3
24 │ slliw a0,a0,24
25 │ sraiw a0,a0,24
26 │ ret
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
gcc/ChangeLog:
* config/riscv/riscv-protos.h (riscv_expand_sssub): Add new func
decl for expanding signed SAT_SUB.
* config/riscv/riscv.cc (riscv_expand_sssub): Add new func impl
for expanding signed SAT_SUB.
* config/riscv/riscv.md (sssub<mode>3): Add new pattern sssub
for scalar signed integer.
