Tamar Christina <tamar.christ...@arm.com> writes:
>> -----Original Message-----
>> From: Richard Sandiford <richard.sandif...@arm.com>
>> Sent: Friday, September 20, 2024 2:10 PM
>> To: Tamar Christina <tamar.christ...@arm.com>
>> Cc: gcc-patches@gcc.gnu.org; nd <n...@arm.com>
>> Subject: Re: [PATCH 3/4][rtl]: simplify boolean vector EQ and NE comparisons
>>
>> Tamar Christina <tamar.christ...@arm.com> writes:
>> >> For variable-sized vectors, I suppose the question is whether the
>> >> first unequal element is found in the minimum vector length, or whether
>> >> it only occurs for larger lengths. In the former case we can fold at
>> >> compile time, but in the latter case we can't.
>> >>
>> >> So we probably do want the loop for variable-length vectors, up to
>> >> constant_lower_bound (CONST_VECTOR_NUNITS (...)).
>> >>
>> >
>> > Doesn't operand_equal already do this? it looks like the VLA handling
>> > In same_vector_encodings_p rejects vectors that are not the same size,
>> > which is good enough for this no? since I'm after strict equality.
>>
>> But what I meant is that for VLA vectors, compile-time equality is
>> a tristate value: yes, no, or maybe.
>>
>> E.g.:
>>
>> { 0, 0, 0, 0, 0, 0, 0, 0, ... }
>>
>> is not equal to
>>
>> { 0, 0, 1, 1, 1, 1, 1, 1, ... }
>>
>> if the runtime VL gives more than 2 elements, but they are equal if
>> the runtime VL gives 2 elements. In this case, we can't fold EQ to
>> false at compile time if the minimum length is 2 elements, but we can
>> if the minimum length is 4 elements.
>>
>> Similarly:
>>
>> { 0, 0, 1, 1, 1, 1, 1, 1, ... }
>>
>> is only conditionally not equal to:
>>
>> { 0, 0, 1, 1, 2, 2, 3, 3, ... }
>>
>> It isn't the case that every encoded value has to be present in every
>> runtime vector. E.g. the series { 0, 1, 2, ... } exists for VNx2DI
>> (for INDEX Z0.D, #0, #1), even though there is never a "2" element for
>> the minimum vector length.
>
> Ah ok... so if I understand correctly, VLA series aren't capped by the VL
> (e.g. representable values) In RTL but represent the base + step only.
> So the series for a VNx2DI and a VNx4SI are the same but what the
> usable bits are is determined by the mode/VL?
Right. For VLA vectors, the vector constant encoding represents an
infinite series and the runtime VL decides how many elements to take
from the series. It's a little more complex than just base + step,
since we allow a leading fixed-length sequence of "arbitrary" values
followed by a series of "regular" values.
But yeah, the "regular" part of the series consists of interleaved linear
series. And some runtime VL might only take the leading "arbitrary"
elements, without digging in to the "regular" part. Or they might
take the base elements without getting as far as using the steps.
Thanks,
Richard
>
> That's really not how I thought they were represented but get why you
> want a loop now...
>
> Tamar.
