Hi, all
The memory attr of some instructions should be 'load', but these is 'none'
currently.
This patch add two new types ssemov2, sseicvt2 for some load instructions that
use memory on operands. So their memory attr will be 'load'.
Bootstrapped and Regtested on x86-64-pc-linux-gnu, OK for trunk?
BRs
Lin
gcc/ChangeLog:
* config/i386/i386.md: Add ssemov2, sseicvt2.
* config/i386/sse.md (sse2_cvtsi2sd): Apply sseicvt2.
(sse2_cvtsi2sdq<round_name>): Ditto.
(vec_set<mode>_0): Apply ssemov2 for 4, 6.
---
gcc/config/i386/i386.md | 11 +++++++----
gcc/config/i386/sse.md | 6 ++++--
2 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index c0441514949..9c2a0aa6112 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -539,10 +539,10 @@ (define_attr "type"
str,bitmanip,
fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,
fxch,fistp,fisttp,frndint,
- sse,ssemov,sseadd,sseadd1,sseiadd,sseiadd1,
+ sse,ssemov,ssemov2,sseadd,sseadd1,sseiadd,sseiadd1,
ssemul,sseimul,ssediv,sselog,sselog1,
sseishft,sseishft1,ssecmp,ssecomi,
- ssecvt,ssecvt1,sseicvt,sseins,
+ ssecvt,ssecvt1,sseicvt,sseicvt2,sseins,
sseshuf,sseshuf1,ssemuladd,sse4arg,
lwp,mskmov,msklog,
mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft"
@@ -560,10 +560,10 @@ (define_attr "unit" "integer,i387,sse,mmx,unknown"
(cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,
fxch,fistp,fisttp,frndint")
(const_string "i387")
- (eq_attr "type" "sse,ssemov,sseadd,sseadd1,sseiadd,sseiadd1,
+ (eq_attr "type" "sse,ssemov,ssemov2,sseadd,sseadd1,sseiadd,sseiadd1,
ssemul,sseimul,ssediv,sselog,sselog1,
sseishft,sseishft1,ssecmp,ssecomi,
- ssecvt,ssecvt1,sseicvt,sseins,
+ ssecvt,ssecvt1,sseicvt,sseicvt2,sseins,
sseshuf,sseshuf1,ssemuladd,sse4arg,mskmov")
(const_string "sse")
(eq_attr "type" "mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")
@@ -858,6 +858,9 @@ (define_attr "memory" "none,load,store,both,unknown"
mmx,mmxmov,mmxcmp,mmxcvt,mskmov,msklog")
(match_operand 2 "memory_operand"))
(const_string "load")
+ (and (eq_attr "type" "ssemov2,sseicvt2")
+ (match_operand 2 "memory_operand"))
+ (const_string "load")
(and (eq_attr "type" "icmov,ssemuladd,sse4arg")
(match_operand 3 "memory_operand"))
(const_string "load")
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 1ae61182d0c..ff4f33b7b63 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -8876,7 +8876,7 @@ (define_insn "sse2_cvtsi2sd"
cvtsi2sd{l}\t{%2, %0|%0, %2}
vcvtsi2sd{l}\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,noavx,avx")
- (set_attr "type" "sseicvt")
+ (set_attr "type" "sseicvt2")
(set_attr "athlon_decode" "double,direct,*")
(set_attr "amdfam10_decode" "vector,double,*")
(set_attr "bdver1_decode" "double,direct,*")
@@ -8898,7 +8898,7 @@ (define_insn "sse2_cvtsi2sdq<round_name>"
cvtsi2sd{q}\t{%2, %0|%0, %2}
vcvtsi2sd{q}\t{%2, <round_op3>%1, %0|%0, %1<round_op3>, %2}"
[(set_attr "isa" "noavx,noavx,avx")
- (set_attr "type" "sseicvt")
+ (set_attr "type" "sseicvt2")
(set_attr "athlon_decode" "double,direct,*")
(set_attr "amdfam10_decode" "vector,double,*")
(set_attr "bdver1_decode" "double,direct,*")
@@ -11808,6 +11808,8 @@ (define_insn "vec_set<mode>_0"
(const_string "imov")
(eq_attr "alternative" "14")
(const_string "fmov")
+ (eq_attr "alternative" "4,6")
+ (const_string "ssemov2")
]
(const_string "ssemov")))
(set (attr "addr")
--
2.31.1
