From: Pan Li <pan2...@intel.com>
This patch would like to add strict check for imm operand of .SAT_ADD
matching. We have no type checking for imm operand in previous, which
may result in unexpected IL to be catched by .SAT_ADD pattern.
We leverage the int_fits_type_p here to make sure the imm operand is
a int type fits the result type of the .SAT_ADD. For example:
Fits uint8_t:
uint8_t a;
uint8_t sum = .SAT_ADD (a, 12);
uint8_t sum = .SAT_ADD (a, 12u);
uint8_t sum = .SAT_ADD (a, 126u);
uint8_t sum = .SAT_ADD (a, 128u);
uint8_t sum = .SAT_ADD (a, 228);
uint8_t sum = .SAT_ADD (a, 223u);
Not fits uint8_t:
uint8_t a;
uint8_t sum = .SAT_ADD (a, -1);
uint8_t sum = .SAT_ADD (a, 256u);
uint8_t sum = .SAT_ADD (a, 257);
The below test suite are passed for this patch:
* The rv64gcv fully regression test.
* The x86 bootstrap test.
* The x86 fully regression test.
gcc/ChangeLog:
* match.pd: Add int_fits_type_p check for .SAT_ADD imm operand.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add test helper macros.
* gcc.target/riscv/sat_u_add_imm-11.c: Adjust test case for imm.
* gcc.target/riscv/sat_u_add_imm-11.c: Ditto.
* gcc.target/riscv/sat_u_add_imm-12.c: Ditto.
* gcc.target/riscv/sat_u_add_imm-15.c: Ditto.
* gcc.target/riscv/sat_u_add_imm-16.c: Ditto.
* gcc.target/riscv/sat_u_add_imm_type_check-1.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-10.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-11.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-12.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-13.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-14.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-15.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-16.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-17.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-18.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-19.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-2.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-20.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-21.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-22.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-23.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-24.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-25.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-26.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-27.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-28.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-29.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-3.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-30.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-31.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-32.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-33.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-34.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-35.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-36.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-37.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-38.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-39.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-4.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-40.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-41.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-42.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-43.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-44.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-45.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-46.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-47.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-48.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-49.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-5.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-50.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-51.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-52.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-6.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-7.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-8.c: New test.
* gcc.target/riscv/sat_u_add_imm_type_check-9.c: New test.
Signed-off-by: Pan Li <pan2...@intel.com>
---
gcc/match.pd | 2 +-
gcc/testsuite/gcc.target/riscv/sat_arith.h | 16 ++++++++++++++++
.../gcc.target/riscv/sat_u_add_imm-11.c | 4 ++--
.../gcc.target/riscv/sat_u_add_imm-12.c | 4 ++--
.../gcc.target/riscv/sat_u_add_imm-15.c | 4 ++--
.../gcc.target/riscv/sat_u_add_imm-16.c | 4 ++--
.../riscv/sat_u_add_imm_type_check-1.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-10.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-11.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-12.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-13.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-14.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-15.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-16.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-17.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-18.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-19.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-2.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-20.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-21.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-22.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-23.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-24.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-25.c | 9 +++++++++
.../riscv/sat_u_add_imm_type_check-26.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-27.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-28.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-29.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-3.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-30.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-31.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-32.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-33.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-34.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-35.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-36.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-37.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-38.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-39.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-4.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-40.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-41.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-42.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-43.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-44.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-45.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-46.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-47.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-48.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-49.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-5.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-50.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-51.c | 9 +++++++++
.../riscv/sat_u_add_imm_type_check-52.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-6.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-7.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-8.c | 8 ++++++++
.../riscv/sat_u_add_imm_type_check-9.c | 8 ++++++++
58 files changed, 443 insertions(+), 9 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-13.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-14.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-15.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-16.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-17.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-18.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-19.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-20.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-21.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-22.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-23.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-24.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-25.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-26.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-27.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-28.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-29.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-30.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-31.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-33.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-34.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-35.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-36.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-37.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-38.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-39.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-40.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-41.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-42.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-43.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-44.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-45.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-46.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-47.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-48.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-49.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-50.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-51.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-52.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-8.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-9.c
diff --git a/gcc/match.pd b/gcc/match.pd
index 65a3aae2243..50f149224a8 100644
--- a/gcc/match.pd
+++ b/gcc/match.pd
@@ -3190,7 +3190,7 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
(cond^ (ne (imagpart (IFN_ADD_OVERFLOW@2 @0 INTEGER_CST@1)) integer_zerop)
integer_minus_onep (realpart @2))
(if (INTEGRAL_TYPE_P (type) && TYPE_UNSIGNED (type)
- && types_match (type, @0))))
+ && types_match (type, @0) && int_fits_type_p (@1, type))))
/* Unsigned saturation sub, case 1 (branch with gt):
SAT_U_SUB = X > Y ? X - Y : 0 */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h
b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 91853b60f59..c6336a114ee 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -90,6 +90,22 @@ sat_u_add_imm##IMM##_##T##_fmt_4 (T x)
\
return __builtin_add_overflow (x, IMM, &ret) == 0 ? ret : -1; \
}
+#define DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_1(T, IMM) \
+T __attribute__((noinline)) \
+sat_u_add_imm_type_check##_##T##_fmt_1 (T x) \
+{ \
+ T ret; \
+ return __builtin_add_overflow (x, IMM, &ret) ? -1 : ret; \
+}
+
+#define DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_2(T, IMM) \
+T __attribute__((noinline)) \
+sat_u_add_imm_type_check##_##T##_fmt_2 (T x) \
+{ \
+ T ret; \
+ return __builtin_add_overflow (x, IMM, &ret) == 0 ? ret : -1; \
+}
+
#define RUN_SAT_U_ADD_IMM_FMT_1(T, x, IMM, expect) \
if (sat_u_add_imm##IMM##_##T##_fmt_1(x) != expect) __builtin_abort ()
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-11.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-11.c
index 43f34b5f3c9..a246e9b1857 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-11.c
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-11.c
@@ -5,7 +5,7 @@
#include "sat_arith.h"
/*
-** sat_u_add_imm7_uint32_t_fmt_3:
+** sat_u_add_imm7u_uint32_t_fmt_3:
** slli\s+[atx][0-9]+,\s*a0,\s*32
** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32
** addi\s+[atx][0-9]+,\s*a0,\s*7
@@ -17,6 +17,6 @@
** sext.w\s+a0,\s*a0
** ret
*/
-DEF_SAT_U_ADD_IMM_FMT_3(uint32_t, 7)
+DEF_SAT_U_ADD_IMM_FMT_3(uint32_t, 7u)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-12.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-12.c
index 561c127f5fa..143f14c3af0 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-12.c
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-12.c
@@ -5,13 +5,13 @@
#include "sat_arith.h"
/*
-** sat_u_add_imm8_uint64_t_fmt_3:
+** sat_u_add_imm8ull_uint64_t_fmt_3:
** addi\s+[atx][0-9]+,\s*a0,\s*8
** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
** neg\s+[atx][0-9]+,\s*[atx][0-9]+
** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
** ret
*/
-DEF_SAT_U_ADD_IMM_FMT_3(uint64_t, 8)
+DEF_SAT_U_ADD_IMM_FMT_3(uint64_t, 8ull)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-15.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-15.c
index eeea574bba2..995a02bffff 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-15.c
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-15.c
@@ -5,7 +5,7 @@
#include "sat_arith.h"
/*
-** sat_u_add_imm7_uint32_t_fmt_4:
+** sat_u_add_imm7u_uint32_t_fmt_4:
** slli\s+[atx][0-9]+,\s*a0,\s*32
** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32
** addi\s+[atx][0-9]+,\s*a0,\s*7
@@ -17,6 +17,6 @@
** sext.w\s+a0,\s*a0
** ret
*/
-DEF_SAT_U_ADD_IMM_FMT_4(uint32_t, 7)
+DEF_SAT_U_ADD_IMM_FMT_4(uint32_t, 7u)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-16.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-16.c
index 307b81589ee..65e5a4a99bb 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-16.c
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-16.c
@@ -5,13 +5,13 @@
#include "sat_arith.h"
/*
-** sat_u_add_imm8_uint64_t_fmt_4:
+** sat_u_add_imm8ull_uint64_t_fmt_4:
** addi\s+[atx][0-9]+,\s*a0,\s*8
** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
** neg\s+[atx][0-9]+,\s*[atx][0-9]+
** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
** ret
*/
-DEF_SAT_U_ADD_IMM_FMT_4(uint64_t, 8)
+DEF_SAT_U_ADD_IMM_FMT_4(uint64_t, 8ull)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-1.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-1.c
new file mode 100644
index 00000000000..db4b0be7538
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_1(uint8_t, 9)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-10.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-10.c
new file mode 100644
index 00000000000..37ec6e9b714
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-10.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_1(uint16_t, 52767)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-11.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-11.c
new file mode 100644
index 00000000000..8dca3b2cb9b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-11.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_1(uint16_t, 65534u)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-12.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-12.c
new file mode 100644
index 00000000000..f3cde55242a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-12.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_1(uint16_t, -3)
+
+/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-13.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-13.c
new file mode 100644
index 00000000000..61834e74452
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-13.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_1(uint16_t, 65549)
+
+/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-14.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-14.c
new file mode 100644
index 00000000000..74e9298361e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-14.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_1(uint16_t, 67732u)
+
+/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-15.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-15.c
new file mode 100644
index 00000000000..f5d60e9a098
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-15.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_1(uint32_t, 91)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-16.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-16.c
new file mode 100644
index 00000000000..e7742b30a9a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-16.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_1(uint32_t, 2147483644u)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-17.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-17.c
new file mode 100644
index 00000000000..1437206b1e0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-17.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_1(uint32_t, 2147483944)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-18.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-18.c
new file mode 100644
index 00000000000..4ef47e23566
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-18.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_1(uint32_t, 4294967293u)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-19.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-19.c
new file mode 100644
index 00000000000..3df6acf2478
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-19.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_1(uint32_t, -3433)
+
+/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-2.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-2.c
new file mode 100644
index 00000000000..ab69971a478
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-2.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_1(uint8_t, 126u)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-20.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-20.c
new file mode 100644
index 00000000000..b504faf0bac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-20.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_1(uint32_t, 4294967342ll)
+
+/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-21.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-21.c
new file mode 100644
index 00000000000..55e56831d10
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-21.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_1(uint32_t, 4994967342ull)
+
+/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-22.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-22.c
new file mode 100644
index 00000000000..fdd686336b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-22.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_1(uint64_t, 439)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-23.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-23.c
new file mode 100644
index 00000000000..f6e9b6bdc38
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-23.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_1(uint64_t, 576460752303423482u)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-24.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-24.c
new file mode 100644
index 00000000000..1d73286776e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-24.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_1(uint64_t, 576460752303483482)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-25.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-25.c
new file mode 100644
index 00000000000..9f8dd6be84c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-25.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_1(uint64_t, 976460752303483482u)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-26.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-26.c
new file mode 100644
index 00000000000..988a557e7a3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-26.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_1(uint64_t, -39294)
+
+/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-27.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-27.c
new file mode 100644
index 00000000000..9b14324e6b3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-27.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_2(uint8_t, 9)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-28.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-28.c
new file mode 100644
index 00000000000..781699c48e2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-28.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_2(uint8_t, 126u)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-29.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-29.c
new file mode 100644
index 00000000000..7aa0720218c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-29.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_2(uint8_t, 129)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-3.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-3.c
new file mode 100644
index 00000000000..ea49c6b9d7f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-3.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_1(uint8_t, 129)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-30.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-30.c
new file mode 100644
index 00000000000..467b9d99823
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-30.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_2(uint8_t, 254u)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-31.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-31.c
new file mode 100644
index 00000000000..6a144a72938
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-31.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_2(uint8_t, -3)
+
+/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-32.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-32.c
new file mode 100644
index 00000000000..2cc1912e47d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-32.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_2(uint8_t, 267)
+
+/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-33.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-33.c
new file mode 100644
index 00000000000..c94716d88eb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-33.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_2(uint8_t, 287u)
+
+/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-34.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-34.c
new file mode 100644
index 00000000000..9b38133c015
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-34.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_2(uint16_t, 9)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-35.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-35.c
new file mode 100644
index 00000000000..4b5c6fa112c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-35.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_2(uint16_t, 32767u)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-36.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-36.c
new file mode 100644
index 00000000000..903df4937b3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-36.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_2(uint16_t, 52767)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-37.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-37.c
new file mode 100644
index 00000000000..ff30c207c23
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-37.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_2(uint16_t, 65534u)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-38.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-38.c
new file mode 100644
index 00000000000..45e06e40c0c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-38.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_2(uint16_t, -3)
+
+/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-39.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-39.c
new file mode 100644
index 00000000000..659352e8244
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-39.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_2(uint16_t, 65549)
+
+/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-4.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-4.c
new file mode 100644
index 00000000000..c9a33edd629
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-4.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_1(uint8_t, 254u)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-40.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-40.c
new file mode 100644
index 00000000000..a16776a0dbb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-40.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_2(uint16_t, 67732u)
+
+/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-41.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-41.c
new file mode 100644
index 00000000000..edcad091d8f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-41.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_2(uint32_t, 91)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-42.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-42.c
new file mode 100644
index 00000000000..8d37bba4f2a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-42.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_2(uint32_t, 2147483644u)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-43.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-43.c
new file mode 100644
index 00000000000..5976d6e67e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-43.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_2(uint32_t, 2147483944)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-44.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-44.c
new file mode 100644
index 00000000000..f19edb2aa83
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-44.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_2(uint32_t, 4294967293u)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-45.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-45.c
new file mode 100644
index 00000000000..0a48acaba8c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-45.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_2(uint32_t, -3433)
+
+/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-46.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-46.c
new file mode 100644
index 00000000000..26d293ea676
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-46.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_2(uint32_t, 4294967342ll)
+
+/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-47.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-47.c
new file mode 100644
index 00000000000..37bf026ce8f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-47.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_2(uint32_t, 4994967342ull)
+
+/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-48.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-48.c
new file mode 100644
index 00000000000..f16c68e2ba5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-48.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_2(uint64_t, 439)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-49.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-49.c
new file mode 100644
index 00000000000..ec2b557758e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-49.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_2(uint64_t, 576460752303423482u)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-5.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-5.c
new file mode 100644
index 00000000000..1e21831ad44
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-5.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_1(uint8_t, -3)
+
+/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-50.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-50.c
new file mode 100644
index 00000000000..752ca6f4388
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-50.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_2(uint64_t, 576460752303483482)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-51.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-51.c
new file mode 100644
index 00000000000..b9fe726d2d3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-51.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_2(uint64_t, 976460752303483482u)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-52.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-52.c
new file mode 100644
index 00000000000..f1afecb4572
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-52.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_2(uint64_t, -39294)
+
+/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-6.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-6.c
new file mode 100644
index 00000000000..03708570551
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-6.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_1(uint8_t, 267)
+
+/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-7.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-7.c
new file mode 100644
index 00000000000..660635ec724
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-7.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_1(uint8_t, 287u)
+
+/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-8.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-8.c
new file mode 100644
index 00000000000..38da62def23
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-8.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_1(uint16_t, 9)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-9.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-9.c
new file mode 100644
index 00000000000..baf81b4b90d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-9.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_TYPE_CHECK_FMT_1(uint16_t, 32767u)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
--
2.43.0
