LGTM
Robin Dapp <rdapp....@gmail.com> 於 2024年8月23日 週五 00:04 寫道：
> Hi,
>
> standard abs synthesis during expand is max (a, -a). This
> expansion has the advantage of avoiding masking and is thus potentially
> faster than the a < 0 ? -a : a synthesis.
>
> Regtested on rv64gcv_zvfh_zvbb.
>
> Regards
> Robin
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md (abs<mode>2): Expand via max (a, -a).
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c: Adjust test
> expectation.
> * gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c: Ditto.
> * gcc.target/riscv/rvv/autovec/vls/abs-2.c: Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c: Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c: Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c: Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c: Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c: Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c: Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c: Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c: Ditto.
> ---
> gcc/config/riscv/autovec.md | 26 ++++++-------------
> .../riscv/rvv/autovec/cond/cond_unary-1.c | 6 +++--
> .../riscv/rvv/autovec/cond/cond_unary-2.c | 6 +++--
> .../riscv/rvv/autovec/cond/cond_unary-3.c | 6 +++--
> .../riscv/rvv/autovec/cond/cond_unary-4.c | 6 +++--
> .../riscv/rvv/autovec/cond/cond_unary-5.c | 6 +++--
> .../riscv/rvv/autovec/cond/cond_unary-6.c | 6 +++--
> .../riscv/rvv/autovec/cond/cond_unary-7.c | 6 +++--
> .../riscv/rvv/autovec/cond/cond_unary-8.c | 6 +++--
> .../riscv/rvv/autovec/unop/abs-rv32gcv.c | 6 ++---
> .../riscv/rvv/autovec/unop/abs-rv64gcv.c | 6 ++---
> .../gcc.target/riscv/rvv/autovec/vls/abs-2.c | 2 +-
> 12 files changed, 47 insertions(+), 41 deletions(-)
>
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index bf1651de60a..6544ac78c9c 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -1073,29 +1073,19 @@ (define_insn_and_split "<optab><mode>2"
> [(set_attr "type" "vialu")])
>
> ;;
> -------------------------------------------------------------------------------
> -;; - [INT] ABS expansion to vmslt and vneg.
> +;; - [INT] ABS expansion to vneg and vmax.
> ;;
> -------------------------------------------------------------------------------
>
> -(define_insn_and_split "abs<mode>2"
> +(define_expand "abs<mode>2"
> [(set (match_operand:V_VLSI 0 "register_operand")
> - (abs:V_VLSI
> - (match_operand:V_VLSI 1 "register_operand")))]
> - "TARGET_VECTOR && can_create_pseudo_p ()"
> - "#"
> - "&& 1"
> - [(const_int 0)]
> + (smax:V_VLSI
> + (match_dup 0)
> + (neg:V_VLSI
> + (match_operand:V_VLSI 1 "register_operand"))))]
> + "TARGET_VECTOR"
> {
> - rtx zero = gen_const_vec_duplicate (<MODE>mode, GEN_INT (0));
> - machine_mode mask_mode = riscv_vector::get_mask_mode (<MODE>mode);
> - rtx mask = gen_reg_rtx (mask_mode);
> - riscv_vector::expand_vec_cmp (mask, LT, operands[1], zero);
> -
> - rtx ops[] = {operands[0], mask, operands[1], operands[1]};
> - riscv_vector::emit_vlmax_insn (code_for_pred (NEG, <MODE>mode),
> - riscv_vector::UNARY_OP_TAMU, ops);
> DONE;
> -}
> -[(set_attr "type" "vector")])
> +})
>
> ;;
> -------------------------------------------------------------------------------
> ;; ---- [FP] Unary operations
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c
> index 2233c6eeecb..4866b221ca4 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c
> @@ -36,8 +36,10 @@
>
> TEST_ALL (DEF_LOOP)
>
> -/* NOTE: int abs operator is converted to vmslt + vneg.v */
> -/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 8
> } } */
> +/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
> +/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 8 } } */
> +/* { dg-final { scan-assembler-times
> {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 4 } } */
> +/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 4
> } } */
> /* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 4
> } } */
> /* { dg-final { scan-assembler-times {\tvfabs\.v\tv[0-9]+,v[0-9]+,v0\.t}
> 3 } } */
> /* { dg-final { scan-assembler-times {\tvfneg\.v\tv[0-9]+,v[0-9]+,v0\.t}
> 3 } } */
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c
> index 4886bff67d8..651df9f8646 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c
> @@ -39,8 +39,10 @@
>
> TEST_ALL (DEF_LOOP)
>
> -/* NOTE: int abs operator is converted to vmslt + vneg.v */
> -/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 8
> } } */
> +/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
> +/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 8 } } */
> +/* { dg-final { scan-assembler-times
> {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 4 } } */
> +/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 4
> } } */
> /* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 4
> } } */
> /* { dg-final { scan-assembler-times {\tvfabs\.v\tv[0-9]+,v[0-9]+,v0\.t}
> 3 } } */
> /* { dg-final { scan-assembler-times {\tvfneg\.v\tv[0-9]+,v[0-9]+,v0\.t}
> 3 } } */
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c
> index a75bde9543a..cc5f7883a64 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c
> @@ -36,8 +36,10 @@
>
> TEST_ALL (DEF_LOOP)
>
> -/* NOTE: int abs operator is converted to vmslt + vneg.v */
> -/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 8
> } } */
> +/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
> +/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 8 } } */
> +/* { dg-final { scan-assembler-times
> {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 4 } } */
> +/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 4
> } } */
> /* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 4
> } } */
> /* { dg-final { scan-assembler-times {\tvfabs\.v\tv[0-9]+,v[0-9]+,v0\.t}
> 3 } } */
> /* { dg-final { scan-assembler-times {\tvfneg\.v\tv[0-9]+,v[0-9]+,v0\.t}
> 3 } } */
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c
> index ef2784bc5d7..b5f83444c5c 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c
> @@ -36,8 +36,10 @@
>
> TEST_ALL (DEF_LOOP)
>
> -/* NOTE: int abs operator is converted to vmslt + vneg.v */
> -/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 8
> } } */
> +/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
> +/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 8 } } */
> +/* { dg-final { scan-assembler-times
> {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 4 } } */
> +/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 4
> } } */
> /* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 4
> } } */
> /* { dg-final { scan-assembler-times {\tvfabs\.v\tv[0-9]+,v[0-9]+,v0\.t}
> 3 } } */
> /* { dg-final { scan-assembler-times {\tvfneg\.v\tv[0-9]+,v[0-9]+,v0\.t}
> 3 } } */
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c
> index 3d90f7bbd8c..76089549fba 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c
> @@ -31,8 +31,10 @@
>
> TEST_ALL (DEF_LOOP)
>
> -/* NOTE: int abs operator is converted to vmslt + vneg.v */
> -/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t}
> 12 } } */
> +/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
> +/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 12 } }
> */
> +/* { dg-final { scan-assembler-times
> {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 6 } } */
> +/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 6
> } } */
> /* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 6
> } } */
> /* NOTE: int abs operator cannot combine the vmerge. */
> /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 6 } } */
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c
> index da9740f536d..6dfb57e52c0 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c
> @@ -34,8 +34,10 @@
>
> TEST_ALL (DEF_LOOP)
>
> -/* NOTE: int abs operator is converted to vmslt + vneg.v */
> -/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t}
> 12 } } */
> +/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
> +/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 12 } }
> */
> +/* { dg-final { scan-assembler-times
> {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 6 } } */
> +/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 6
> } } */
> /* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 6
> } } */
> /* NOTE: int abs operator cannot combine the vmerge. */
> /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 6 } } */
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c
> index e0a799460f8..ca24a332055 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c
> @@ -31,8 +31,10 @@
>
> TEST_ALL (DEF_LOOP)
>
> -/* NOTE: int abs operator is converted to vmslt + vneg.v */
> -/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t}
> 12 } } */
> +/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
> +/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 12 } }
> */
> +/* { dg-final { scan-assembler-times
> {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 6 } } */
> +/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 6
> } } */
> /* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 6
> } } */
> /* NOTE: int abs operator cannot combine the vmerge. */
> /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 6 } } */
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c
> index a70a1a32bdc..7be4b373a2c 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c
> @@ -31,8 +31,10 @@
>
> TEST_ALL (DEF_LOOP)
>
> -/* NOTE: int abs operator is converted to vmslt + vneg.v */
> -/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t}
> 12 } } */
> +/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
> +/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 12 } }
> */
> +/* { dg-final { scan-assembler-times
> {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 6 } } */
> +/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 6
> } } */
> /* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 6
> } } */
> /* NOTE: int abs operator cannot combine the vmerge. */
> /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 6 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c
> index 85751912e33..3f62d0eafe7 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c
> @@ -3,7 +3,7 @@
>
> #include "abs-template.h"
>
> -/* { dg-final { scan-assembler-times {\tvseti?vli\s+[a-z0-9,]+,ta,mu} 4 }
> } */
> -/* { dg-final { scan-assembler-times {\tvmslt\.vi} 4 } } */
> -/* { dg-final { scan-assembler-times {\tvneg.v\sv[0-9]+,v[0-9]+,v0\.t} 4
> } } */
> +/* { dg-final { scan-assembler-times {\tvseti?vli\s+[a-z0-9,]+,ta,ma} 7 }
> } */
> +/* { dg-final { scan-assembler-times {\tvneg\.v} 4 } } */
> +/* { dg-final { scan-assembler-times
> {\tvmax\.vv\sv[0-9]+,v[0-9]+,v[0-9]+} 4 } } */
> /* { dg-final { scan-assembler-times {\tvfabs.v} 3 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c
> index d1bd43ae9db..64302191cda 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c
> @@ -3,7 +3,7 @@
>
> #include "abs-template.h"
>
> -/* { dg-final { scan-assembler-times {\tvseti?vli\s+[a-z0-9,]+,ta,mu} 4 }
> } */
> -/* { dg-final { scan-assembler-times {\tvmslt\.vi} 4 } } */
> -/* { dg-final { scan-assembler-times {\tvneg.v\sv[0-9]+,v[0-9]+,v0\.t} 4
> } } */
> +/* { dg-final { scan-assembler-times {\tvseti?vli\s+[a-z0-9,]+,ta,ma} 7 }
> } */
> +/* { dg-final { scan-assembler-times {\tvneg\.v} 4 } } */
> +/* { dg-final { scan-assembler-times
> {\tvmax\.vv\sv[0-9]+,v[0-9]+,v[0-9]+} 4 } } */
> /* { dg-final { scan-assembler-times {\tvfabs.v} 3 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-2.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-2.c
> index 5389a55a97f..510939a0c15 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-2.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-2.c
> @@ -46,7 +46,7 @@ DEF_OP_V (neg, 256, int64_t, __builtin_abs)
> DEF_OP_V (neg, 512, int64_t, __builtin_abs)
>
> /* { dg-final { scan-assembler-times {vneg\.v} 38 } } */
> -/* { dg-final { scan-assembler-times {vmslt\.vi} 38 } } */
> +/* { dg-final { scan-assembler-times {vmax\.vv} 38 } } */
> /* { dg-final { scan-assembler-not {csrr} } } */
> /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
> /* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
> --
> 2.46.0
>
>
