On Wed, 21 Aug 2024, Robin Dapp wrote: > > > > When predicating a load we implicitly assume that the else value is > > > > zero. In order to formalize this this patch queries the target for > > > > its supported else operand and uses that for the maskload call. > > > > Subsequently, if the else operand is nonzero, a cond_expr enforcing > > > > a zero else value is emitted. > > > > Why? I don't think the vectorizer relies on a particular else > > value? I'd say it would be appropriate for if-conversion to > > use "ANY" and for the vectorizer to then pick a supported > > version and/or enforce the else value it needs via a blend? > > In PR115336 we have something like > > _Bool iftmp.0_113; > _Bool iftmp.0_114; > iftmp.0_113 = .MASK_LOAD (_170, 8B, _169, _171(D)); > iftmp.0_114 = _47 | iftmp.0_113; > > which assumes zeroing.
I see - is that some trick ifcvt performs? I can't immediately see the connection to the PR and it only contains RISC-V assembly analysis. > In order to circumvent that we could use COND_IOR > but I suppose that wouldn't be optimized away even on targets that zero > masked elements? "ANY" would seem to be wrong here. What I was trying to say is that of course any transform we perform that requires zero-masking should either make .MAKS_LOAD perform that or add a COND_EXPR. But it shouldn't be required to make all .MASK_LOADs be zero-masked, no? I'm of course fine if you think that's the best way for RISC-V given other targets are likely unaffected as they can perform zero-masking. > So instead, right now the flow is to emit a COND_EXPR after the MASK_LOAD > here if the target does not zero and have the vectorizer vectorize it into > a blend (or something else if the surrounding code allows). > > What I didn't do (in the posted version, just locally) is an explicit > VEC_COND_EXPR after each masked (gather/load lanes) call the vectorizer > does. Do we need that? AFAICT loop masking (be it len style or > fully-masked style) should be safe. Well, why should we need that? There seem to be the assumption that .MASK_LOAD is zero-masked in very few places (PR115336, but not identified there), if we'd assume this everywhere there would be way more issues with RISC-V? For example when we do loop masking I think we elide .COND_op for "safe" operations. But even that doesn't assume zero-masking. Richard.
