From: yulong <shiyul...@iscas.ac.cn> This patch try to fix a bug[116347]. I change the name of the micro-arch, because I think micro-arch and core have the same name that caused the error.
gcc/ChangeLog: * config/riscv/riscv-cores.def (RISCV_TUNE): Rename. (RISCV_CORE): Ditto. --- gcc/config/riscv/riscv-cores.def | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index 2f5efe3be86..e9fc63625fe 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -39,8 +39,8 @@ RISCV_TUNE("sifive-5-series", generic, rocket_tune_info) RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info) RISCV_TUNE("sifive-p400-series", sifive_p400, sifive_p400_tune_info) RISCV_TUNE("sifive-p600-series", sifive_p600, sifive_p600_tune_info) -RISCV_TUNE("thead-c906", generic, thead_c906_tune_info) -RISCV_TUNE("xiangshan-nanhu", xiangshan, xiangshan_nanhu_tune_info) +RISCV_TUNE("thead-c906-series", generic, thead_c906_tune_info) +RISCV_TUNE("xiangshan-nanhu-series", xiangshan, xiangshan_nanhu_tune_info) RISCV_TUNE("generic-ooo", generic_ooo, generic_ooo_tune_info) RISCV_TUNE("size", generic, optimize_size_tune_info) @@ -90,10 +90,10 @@ RISCV_CORE("sifive-p670", "rv64imafdcv_za64rs_zic64b_zicbom_zicbop_zicboz_" RISCV_CORE("thead-c906", "rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_" "xtheadcondmov_xtheadfmemidx_xtheadmac_" "xtheadmemidx_xtheadmempair_xtheadsync", - "thead-c906") + "thead-c906-series") RISCV_CORE("xiangshan-nanhu", "rv64imafdc_zba_zbb_zbc_zbs_" "zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_" "svinval_zicbom_zicboz", - "xiangshan-nanhu") + "xiangshan-nanhu-series") #undef RISCV_CORE -- 2.34.1