LGTM, thanks for fixing that :)
On Wed, Aug 14, 2024 at 2:06 PM 曾治金 <zhijin.z...@spacemit.com> wrote:
>
> This patch is to fix the bug (BugId:116305) introduced by the commit
> bd93ef for risc-v target.
>
> The commit bd93ef changes the chunk_num from 1 to TARGET_MIN_VLEN/128
> if TARGET_MIN_VLEN is larger than 128 in riscv_convert_vector_bits. So
> it changes the value of BYTES_PER_RISCV_VECTOR. For example, before
> merging the commit bd93ef and if TARGET_MIN_VLEN is 256, the value
> of BYTES_PER_RISCV_VECTOR should be [8, 8], but now [16, 16]. The value
> of riscv_bytes_per_vector_chunk and BYTES_PER_RISCV_VECTOR are no longer
> equal.
>
> Prologue will use BYTES_PER_RISCV_VECTOR.coeffs[1] to estimate the vlenb
> register value in riscv_legitimize_poly_move, and dwarf2cfi will also
> get the estimated vlenb register value in riscv_dwarf_poly_indeterminate_value
> to calculate the number of times to multiply the vlenb register value.
>
> So need to change the factor from riscv_bytes_per_vector_chunk to
> BYTES_PER_RISCV_VECTOR, otherwise we will get the incorrect dwarf
> information. The incorrect example as follow:
>
> ```
> csrr t0,vlenb
> slli t1,t0,1
> sub sp,sp,t1
>
> .cfi_escape 0xf,0xb,0x72,0,0x92,0xa2,0x38,0,0x34,0x1e,0x23,0x50,0x22
> ```
>
> The sequence '0x92,0xa2,0x38,0' means the vlenb register, '0x34' means
> the literal 4, '0x1e' means the multiply operation. But in fact, the
> vlenb register value just need to multiply the literal 2.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_dwarf_poly_indeterminate_value):
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/scalable_vector_cfi.c: New test.
>
> Signed-off-by: Zhijin Zeng <zhijin.z...@spacemit.com>
> ---
> gcc/config/riscv/riscv.cc | 4 +--
> .../riscv/rvv/base/scalable_vector_cfi.c | 32 +++++++++++++++++++
> 2 files changed, 34 insertions(+), 2 deletions(-)
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/base/scalable_vector_cfi.c
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 5fe4273beb7..e740fc159dd 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -10773,12 +10773,12 @@ static unsigned int
> riscv_dwarf_poly_indeterminate_value (unsigned int i, unsigned int *factor,
> int *offset)
> {
> - /* Polynomial invariant 1 == (VLENB / riscv_bytes_per_vector_chunk) - 1.
> + /* Polynomial invariant 1 == (VLENB / BYTES_PER_RISCV_VECTOR) - 1.
> 1. TARGET_MIN_VLEN == 32, polynomial invariant 1 == (VLENB / 4) - 1.
> 2. TARGET_MIN_VLEN > 32, polynomial invariant 1 == (VLENB / 8) - 1.
> */
> gcc_assert (i == 1);
> - *factor = riscv_bytes_per_vector_chunk;
> + *factor = BYTES_PER_RISCV_VECTOR.coeffs[1];
> *offset = 1;
> return RISCV_DWARF_VLENB;
> }
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalable_vector_cfi.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/scalable_vector_cfi.c
> new file mode 100644
> index 00000000000..184da10caf3
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalable_vector_cfi.c
> @@ -0,0 +1,32 @@
> +/* { dg-do compile } */
> +/* { dg-options "-g -O3 -march=rv64gcv -mabi=lp64d" } */
> +/* { dg-skip-if "" { *-*-* } {"-O2" "-O1" "-O0" "-Og" "-Oz" "-flto"} } */
> +/* { dg-final { scan-assembler {cfi_escape .*0x92,0xa2,0x38,0,0x32,0x1e} } }
> */
> +
> +#include "riscv_vector.h"
> +
> +#define PI_2 1.570796326795
> +
> +extern void func(float *result);
> +
> +void test(const float *ys, const float *xs, float *result, size_t length) {
> + size_t gvl = __riscv_vsetvlmax_e32m2();
> + vfloat32m2_t vpi2 = __riscv_vfmv_v_f_f32m2(PI_2, gvl);
> +
> + for(size_t i = 0; i < length;) {
> + gvl = __riscv_vsetvl_e32m2(length - i);
> + vfloat32m2_t y = __riscv_vle32_v_f32m2(ys, gvl);
> + vfloat32m2_t x = __riscv_vle32_v_f32m2(xs, gvl);
> + vbool16_t mask0 = __riscv_vmflt_vv_f32m2_b16(x, y, gvl);
> + vfloat32m2_t fixpi = __riscv_vfrsub_vf_f32m2_mu(mask0, vpi2, vpi2,
> 0, gvl);
> +
> + __riscv_vse32_v_f32m2(result, fixpi, gvl);
> +
> + func(result);
> +
> + i += gvl;
> + ys += gvl;
> + xs += gvl;
> + result += gvl;
> + }
> +}
> --
> 2.34.1
>
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