This fixes the remainder of the typos I found when reading various parts of the
RISC-V backend.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (legitimize_move): extrac -> extract.
(expand_vec_cmp_float): Remove duplicate vmnor.mm.
* config/riscv/riscv-vector-builtins.cc: ins -> insns.
* config/riscv/riscv.cc (riscv_init_machine_status): mwrvv -> mrvv.
* config/riscv/vector-iterators.md: RVVM8QImde -> RVVM8QImode
* config/riscv/vector.md: Replaced non-existant vsetivl with vsetivli.
Signed-off-by: Patrick O'Neill <patr...@rivosinc.com>
---
I split these comment changes out so they can be reviewed more closely. I tried
to figure out the intended meaning behind the comments (eg. extrac) but it's
possible I got some wrong.
---
gcc/config/riscv/riscv-v.cc | 6 +++---
gcc/config/riscv/riscv-vector-builtins.cc | 4 ++--
gcc/config/riscv/riscv.cc | 2 +-
gcc/config/riscv/vector-iterators.md | 2 +-
gcc/config/riscv/vector.md | 2 +-
5 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 577e8c8315c..90a156221af 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1552,8 +1552,8 @@ legitimize_move (rtx dest, rtx *srcp)
{
if (GET_MODE_NUNITS (mode).to_constant () <= 31)
{
- /* For NUNITS <= 31 VLS modes, we don't need extrac
- scalar regisers so we apply the naive (set (op0) (op1)) pattern. */
+ /* For NUNITS <= 31 VLS modes, we don't need extract
+ scalar registers so we apply the naive (set (op0) (op1)) pattern.
*/
if (can_create_pseudo_p ())
{
/* Need to force register if mem <- !reg. */
@@ -2900,7 +2900,7 @@ expand_vec_cmp_float (rtx target, rtx_code code, rtx op0,
rtx op1,
}
/* We use one_cmpl<mode>2 to make Combine PASS to combine mask instructions
- into: vmand.mm/vmnor.mm/vmnand.mm/vmnor.mm/vmxnor.mm. */
+ into: vmand.mm/vmnor.mm/vmnand.mm/vmxnor.mm. */
emit_insn (gen_rtx_SET (target, gen_rtx_NOT (mask_mode, eq0)));
return false;
}
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
b/gcc/config/riscv/riscv-vector-builtins.cc
index 7d8a289c80b..3d73514ffb0 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -2765,7 +2765,7 @@ static CONSTEXPR const rvv_op_info
all_v_scalar_ptr_index_ops
scalar_ptr_index_args /* Args */};
/* A static operand information for vector_type func (vector_type).
- Some ins just supports SEW=32, such as crypto vectol Zvkg extension.
+ Some insns just supports SEW=32, such as the crypto vector Zvkg extension.
* function registration. */
static CONSTEXPR const rvv_arg_type_info vs_lmul_x2_args[]
= {rvv_arg_type_info (RVV_BASE_vlmul_ext_x2),
@@ -2838,7 +2838,7 @@ static CONSTEXPR const rvv_op_info
u_vvs_crypto_sew32_lmul_x16_ops
vs_lmul_x16_args /* Args */};
/* A static operand information for vector_type func (vector_type).
- Some ins just supports SEW=64, such as crypto vectol Zvbc extension
+ Some insns just supports SEW=64, such as the crypto vector Zvbc extension
vclmul.vv, vclmul.vx.
* function registration. */
static CONSTEXPR const rvv_op_info u_vvv_crypto_sew64_ops
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index dabcbc3c3f3..9f60d5bfde4 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -9615,7 +9615,7 @@ riscv_init_machine_status (void)
return ggc_cleared_alloc<machine_function> ();
}
-/* Return the VLEN value associated with -march and -mwrvv-vector-bits.
+/* Return the VLEN value associated with -march and -mrvv-vector-bits.
TODO: So far we only support length-agnostic value. */
static poly_uint16
riscv_convert_vector_chunks (struct gcc_options *opts)
diff --git a/gcc/config/riscv/vector-iterators.md
b/gcc/config/riscv/vector-iterators.md
index 5409e9af81a..cbbd248c9bb 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -783,7 +783,7 @@
;;
;; In gather/scatter expand, we need to sign/zero extend the index mode into
vector
;; Pmode, so we need to check whether vector Pmode is available.
-;; E.g. when index mode = RVVM8QImde and Pmode = SImode, if it is not
zero_extend or
+;; E.g. when index mode = RVVM8QImode and Pmode = SImode, if it is not
zero_extend or
;; scalar != 1, such gather/scatter is not allowed since we don't have
RVVM32SImode.
(define_mode_iterator RATIO64 [
(RVVMF8QI "TARGET_MIN_VLEN > 32")
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 6f2225d0f3f..203a41fbde3 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1520,7 +1520,7 @@
;; ---- 6. Configuration-Setting Instructions
;; -----------------------------------------------------------------
;; Includes:
-;; - 6.1 vsetvli/vsetivl/vsetvl instructions
+;; - 6.1 vsetvli/vsetivli/vsetvl instructions
;; -----------------------------------------------------------------
;; we don't define vsetvli as unspec_volatile which has side effects.
--
2.34.1
