gcc/ChangeLog:
* config/riscv/sync-rvwmo.md: Add conditional length attributes.
* config/riscv/sync-ztso.md: Ditto.
* config/riscv/sync.md: Fix incorrect insn length attributes and
reformat existing conditional checks.
Signed-off-by: Patrick O'Neill <patr...@rivosinc.com>
---
gcc/config/riscv/sync-rvwmo.md | 10 ++++++++--
gcc/config/riscv/sync-ztso.md | 9 +++++++--
gcc/config/riscv/sync.md | 10 ++++++----
3 files changed, 21 insertions(+), 8 deletions(-)
diff --git a/gcc/config/riscv/sync-rvwmo.md b/gcc/config/riscv/sync-rvwmo.md
index 5db94c8c27f..e26f53ccd3e 100644
--- a/gcc/config/riscv/sync-rvwmo.md
+++ b/gcc/config/riscv/sync-rvwmo.md
@@ -68,7 +68,10 @@
return "<load>\t%0,%1";
}
[(set_attr "type" "multi")
- (set (attr "length") (const_int 12))])
+ (set (attr "length")
+ (symbol_ref "(is_mm_seq_cst (memmodel_from_int (INTVAL (operands[2])))
? 12
+ : is_mm_acquire (memmodel_from_int (INTVAL
(operands[2]))) ? 8
+ : 4)"))])
;; Implement atomic stores with conservative fences.
;; This allows us to be compatible with the ISA manual Table A.6 and Table A.7.
@@ -94,4 +97,7 @@
return "<store>\t%z1,%0";
}
[(set_attr "type" "multi")
- (set (attr "length") (const_int 12))])
+ (set (attr "length")
+ (symbol_ref "(is_mm_seq_cst (memmodel_from_int (INTVAL (operands[2])))
? 12
+ : is_mm_release (memmodel_from_int (INTVAL
(operands[2]))) ? 8
+ : 4)"))])
diff --git a/gcc/config/riscv/sync-ztso.md b/gcc/config/riscv/sync-ztso.md
index f99a21b45ca..7121b97083f 100644
--- a/gcc/config/riscv/sync-ztso.md
+++ b/gcc/config/riscv/sync-ztso.md
@@ -58,7 +58,10 @@
return "<load>\t%0,%1";
}
[(set_attr "type" "multi")
- (set (attr "length") (const_int 12))])
+ (set (attr "length")
+ (symbol_ref "(is_mm_seq_cst (memmodel_from_int (INTVAL (operands[2])))
? 8
+ : 4)"))])
+
(define_insn "atomic_store_ztso<mode>"
[(set (match_operand:ANYI 0 "memory_operand" "=A")
@@ -78,4 +81,6 @@
return "<store>\t%z1,%0";
}
[(set_attr "type" "multi")
- (set (attr "length") (const_int 8))])
+ (set (attr "length")
+ (symbol_ref "(is_mm_seq_cst (memmodel_from_int (INTVAL (operands[2])))
? 8
+ : 4)"))])
diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index 0c493fea828..aa0c20446f4 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -199,7 +199,7 @@
"bnez\t%4, 1b";
}
[(set_attr "type" "atomic")
- (set (attr "length") (const_int 20))])
+ (set (attr "length") (const_int 16))])
(define_insn "subword_atomic_fetch_strong_<atomic_optab>"
[(set (match_operand:SI 0 "register_operand" "=&r") ;; old value
at mem
@@ -416,7 +416,7 @@
"mv\t%0, %4";
}
[(set_attr "type" "atomic")
- (set (attr "length") (const_int 20))])
+ (set (attr "length") (const_int 16))])
(define_expand "atomic_exchange<mode>"
[(match_operand:SHORT 0 "register_operand") ;; old value at mem
@@ -560,7 +560,8 @@
}
[(set_attr "type" "atomic")
(set (attr "length")
- (symbol_ref "is_mm_seq_cst(memmodel_from_int(INTVAL (operands[5]))) ?
8 : 4"))])
+ (symbol_ref "(is_mm_seq_cst (memmodel_from_int (INTVAL (operands[5])))
? 8
+ : 4)"))])
(define_expand "atomic_compare_and_swap<mode>"
[(match_operand:SI 0 "register_operand" "") ;; bool output
@@ -646,7 +647,8 @@
}
[(set_attr "type" "atomic")
(set (attr "length")
- (symbol_ref "is_mm_seq_cst(memmodel_from_int(INTVAL (operands[5]))) ?
8 : 4"))])
+ (symbol_ref "(is_mm_seq_cst (memmodel_from_int (INTVAL (operands[5])))
? 8
+ : 4)"))])
(define_expand "atomic_compare_and_swap<mode>"
[(match_operand:SI 0 "register_operand") ;; bool output
--
2.34.1
