2024-07-31 03:10 Jeff Law <jeffreya...@gmail.com> wrote:
>
>
>
>On 7/28/24 7:58 PM, Xiao Zeng wrote:
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/riscv/pr105314-rtl.c: Skip zicond.
>> * gcc.target/riscv/pr105314-rtl32.c: Dotto.
>> * gcc.target/riscv/pr105314.c: Dotto.
>Why do you want to skip zicond for this test?
Yes, I should provide as detailed a description as possible for each submitted
patch.
>
>Jeff
riscv64-unknown-linux-gnu-gcc -O2 -march=rv64gc_zicond -mabi=lp64d
../gcc/testsuite/gcc.target/riscv/pr105314.c -fdump-rtl-ce1 -S -o pr105314.c.S
This output will be obtained:
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
;; Function foo (foo, funcdef_no=0, decl_uid=2299, cgraph_uid=1, symbol_order=0)
0 registers.
6 basic blocks, 6 edges.
(note 8 0 2 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn 2 8 4 2 (set (reg/v:DI 135 [ a ])
(reg:DI 10 a0 [ a ]))
"../gcc/testsuite/gcc.target/riscv/pr105314.c":8:1 275 {*movdi_64bit}
(expr_list:REG_DEAD (reg:DI 10 a0 [ a ])
(nil)))
(insn 4 2 5 2 (set (reg/v:DI 137 [ c ])
(reg:DI 12 a2 [ c ]))
"../gcc/testsuite/gcc.target/riscv/pr105314.c":8:1 275 {*movdi_64bit}
(expr_list:REG_DEAD (reg:DI 12 a2 [ c ])
(nil)))
(note 5 4 10 2 NOTE_INSN_FUNCTION_BEG)
(jump_insn 10 5 11 2 (set (pc)
(if_then_else (ne (reg/v:DI 137 [ c ])
(const_int 0 [0]))
(label_ref:DI 23)
(pc))) "../gcc/testsuite/gcc.target/riscv/pr105314.c":9:6 352
{*branchdi}
(expr_list:REG_DEAD (reg/v:DI 137 [ c ])
(int_list:REG_BR_PROB 536870916 (nil)))
-> 23)
(note 11 10 6 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(insn 6 11 23 3 (set (reg/v:DI 134 [ <retval> ])
(reg/v:DI 135 [ a ]))
"../gcc/testsuite/gcc.target/riscv/pr105314.c":9:6 275 {*movdi_64bit}
(expr_list:REG_DEAD (reg/v:DI 135 [ a ])
(nil)))
(code_label 23 6 22 4 3 (nil) [1 uses])
(note 22 23 7 4 [bb 4] NOTE_INSN_BASIC_BLOCK)
(insn 7 22 16 4 (set (reg/v:DI 134 [ <retval> ])
(const_int 0 [0])) "../gcc/testsuite/gcc.target/riscv/pr105314.c":10:7
275 {*movdi_64bit}
(nil))
(code_label 16 7 19 5 1 (nil) [0 uses])
(note 19 16 17 5 [bb 5] NOTE_INSN_BASIC_BLOCK)
(insn 17 19 18 5 (set (reg/i:DI 10 a0)
(reg/v:DI 134 [ <retval> ]))
"../gcc/testsuite/gcc.target/riscv/pr105314.c":12:1 275 {*movdi_64bit}
(expr_list:REG_DEAD (reg/v:DI 134 [ <retval> ])
(nil)))
(insn 18 17 0 5 (use (reg/i:DI 10 a0))
"../gcc/testsuite/gcc.target/riscv/pr105314.c":12:1 -1
(nil))
try_optimize_cfg iteration 1
;; 1 loops found
;;
;; Loop 0
;; header 0, latch 1
;; depth 0, outer -1
;; nodes: 0 1 2 3 4 5
;; 2 succs { 4 3 }
;; 3 succs { 5 }
;; 4 succs { 5 }
;; 5 succs { 1 }
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
IF-THEN-ELSE-JOIN block found, pass 1, test 2, then 3, else 4, join 5
scanning new insn with uid = 25.
if-conversion succeeded through noce_try_cmove
deleting insn with uid = 7.
deleting block 4
Removing jump 10.
deleting insn with uid = 10.
deleting insn with uid = 6.
deleting block 3
Merging block 5 into block 2...
changing bb of uid 19
changing bb of uid 17
from 5 to 2
changing bb of uid 18
from 5 to 2
Merged blocks 2 and 5.
Conversion succeeded on pass 1.
foo
Dataflow summary:
;; fully invalidated by EH 0 [zero] 1 [ra] 3 [gp] 4 [tp] 5 [t0] 6 [t1] 7
[t2] 10 [a0] 11 [a1] 12 [a2] 13 [a3] 14 [a4] 15 [a5] 16 [a6] 17 [a7] 28 [t3] 29
[t4] 30 [t5] 31 [t6] 32 [ft0] 33 [ft1] 34 [ft2] 35 [ft3] 36 [ft4] 37 [ft5] 38
[ft6] 39 [ft7] 42 [fa0] 43 [fa1] 44 [fa2] 45 [fa3] 46 [fa4] 47 [fa5] 48 [fa6]
49 [fa7] 60 [ft8] 61 [ft9] 62 [ft10] 63 [ft11] 66 [vl] 67 [vtype] 68 [vxrm] 69
[frm] 70 [vxsat] 71 [N/A] 72 [N/A] 73 [N/A] 74 [N/A] 75 [N/A] 76 [N/A] 77 [N/A]
78 [N/A] 79 [N/A] 80 [N/A] 81 [N/A] 82 [N/A] 83 [N/A] 84 [N/A] 85 [N/A] 86
[N/A] 87 [N/A] 88 [N/A] 89 [N/A] 90 [N/A] 91 [N/A] 92 [N/A] 93 [N/A] 94 [N/A]
95 [N/A] 96 [v0] 97 [v1] 98 [v2] 99 [v3] 100 [v4] 101 [v5] 102 [v6] 103 [v7]
104 [v8] 105 [v9] 106 [v10] 107 [v11] 108 [v12] 109 [v13] 110 [v14] 111 [v15]
112 [v16] 113 [v17] 114 [v18] 115 [v19] 116 [v20] 117 [v21] 118 [v22] 119 [v23]
120 [v24] 121 [v25] 122 [v26] 123 [v27] 124 [v28] 125 [v29] 126 [v30] 127 [v31]
;; hardware regs used 2 [sp] 64 [arg] 65 [frame]
;; regular block artificial uses 2 [sp] 8 [s0] 64 [arg] 65 [frame]
;; eh block artificial uses 2 [sp] 8 [s0] 64 [arg] 65 [frame]
;; entry block defs 1 [ra] 2 [sp] 8 [s0] 10 [a0] 11 [a1] 12 [a2] 13 [a3]
14 [a4] 15 [a5] 16 [a6] 17 [a7] 42 [fa0] 43 [fa1] 44 [fa2] 45 [fa3] 46 [fa4] 47
[fa5] 48 [fa6] 49 [fa7] 64 [arg] 65 [frame]
;; exit block uses 1 [ra] 2 [sp] 8 [s0] 10 [a0] 65 [frame]
;; regs ever live 10 [a0] 12 [a2]
;; ref usage r1={1d,1u} r2={1d,2u} r8={1d,2u} r10={2d,3u} r11={1d}
r12={1d,1u} r13={1d} r14={1d} r15={1d} r16={1d} r17={1d} r42={1d} r43={1d}
r44={1d} r45={1d} r46={1d} r47={1d} r48={1d} r49={1d} r64={1d,1u} r65={1d,2u}
r134={1d,1u} r135={1d,1u} r137={1d,1u}
;; total ref usage 40{25d,15u,0e} in 5{5 regular + 0 call} insns.
(note 8 0 2 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn 2 8 4 2 (set (reg/v:DI 135 [ a ])
(reg:DI 10 a0 [ a ]))
"../gcc/testsuite/gcc.target/riscv/pr105314.c":8:1 275 {*movdi_64bit}
(expr_list:REG_DEAD (reg:DI 10 a0 [ a ])
(nil)))
(insn 4 2 5 2 (set (reg/v:DI 137 [ c ])
(reg:DI 12 a2 [ c ]))
"../gcc/testsuite/gcc.target/riscv/pr105314.c":8:1 275 {*movdi_64bit}
(expr_list:REG_DEAD (reg:DI 12 a2 [ c ])
(nil)))
(note 5 4 25 2 NOTE_INSN_FUNCTION_BEG)
(insn 25 5 17 2 (set (reg/v:DI 134 [ <retval> ])
(if_then_else:DI (ne (reg/v:DI 137 [ c ])
(const_int 0 [0]))
(const_int 0 [0])
(reg/v:DI 135 [ a ])))
"../gcc/testsuite/gcc.target/riscv/pr105314.c":9:6 32520 {*czero.nez.didi}
(nil))
(insn 17 25 18 2 (set (reg/i:DI 10 a0)
(reg/v:DI 134 [ <retval> ]))
"../gcc/testsuite/gcc.target/riscv/pr105314.c":12:1 275 {*movdi_64bit}
(expr_list:REG_DEAD (reg/v:DI 134 [ <retval> ])
(nil)))
(insn 18 17 0 2 (use (reg/i:DI 10 a0))
"../gcc/testsuite/gcc.target/riscv/pr105314.c":12:1 -1
(nil))
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
df_worklist_dataflow_doublequeue: n_basic_blocks 3 n_edges 2 count 3 ( 1)
df_worklist_dataflow_doublequeue: n_basic_blocks 3 n_edges 2 count 3 ( 1)
========== Pass 2 ==========
========== no more changes
1 possible IF blocks searched.
1 IF blocks converted.
3 true changes made.
try_optimize_cfg iteration 1
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
foo
Dataflow summary:
;; fully invalidated by EH 0 [zero] 1 [ra] 3 [gp] 4 [tp] 5 [t0] 6 [t1] 7
[t2] 10 [a0] 11 [a1] 12 [a2] 13 [a3] 14 [a4] 15 [a5] 16 [a6] 17 [a7] 28 [t3] 29
[t4] 30 [t5] 31 [t6] 32 [ft0] 33 [ft1] 34 [ft2] 35 [ft3] 36 [ft4] 37 [ft5] 38
[ft6] 39 [ft7] 42 [fa0] 43 [fa1] 44 [fa2] 45 [fa3] 46 [fa4] 47 [fa5] 48 [fa6]
49 [fa7] 60 [ft8] 61 [ft9] 62 [ft10] 63 [ft11] 66 [vl] 67 [vtype] 68 [vxrm] 69
[frm] 70 [vxsat] 71 [N/A] 72 [N/A] 73 [N/A] 74 [N/A] 75 [N/A] 76 [N/A] 77 [N/A]
78 [N/A] 79 [N/A] 80 [N/A] 81 [N/A] 82 [N/A] 83 [N/A] 84 [N/A] 85 [N/A] 86
[N/A] 87 [N/A] 88 [N/A] 89 [N/A] 90 [N/A] 91 [N/A] 92 [N/A] 93 [N/A] 94 [N/A]
95 [N/A] 96 [v0] 97 [v1] 98 [v2] 99 [v3] 100 [v4] 101 [v5] 102 [v6] 103 [v7]
104 [v8] 105 [v9] 106 [v10] 107 [v11] 108 [v12] 109 [v13] 110 [v14] 111 [v15]
112 [v16] 113 [v17] 114 [v18] 115 [v19] 116 [v20] 117 [v21] 118 [v22] 119 [v23]
120 [v24] 121 [v25] 122 [v26] 123 [v27] 124 [v28] 125 [v29] 126 [v30] 127 [v31]
;; hardware regs used 2 [sp] 64 [arg] 65 [frame]
;; regular block artificial uses 2 [sp] 8 [s0] 64 [arg] 65 [frame]
;; eh block artificial uses 2 [sp] 8 [s0] 64 [arg] 65 [frame]
;; entry block defs 1 [ra] 2 [sp] 8 [s0] 10 [a0] 11 [a1] 12 [a2] 13 [a3]
14 [a4] 15 [a5] 16 [a6] 17 [a7] 42 [fa0] 43 [fa1] 44 [fa2] 45 [fa3] 46 [fa4] 47
[fa5] 48 [fa6] 49 [fa7] 64 [arg] 65 [frame]
;; exit block uses 1 [ra] 2 [sp] 8 [s0] 10 [a0] 65 [frame]
;; regs ever live 10 [a0] 12 [a2]
;; ref usage r1={1d,1u} r2={1d,2u} r8={1d,2u} r10={2d,3u} r11={1d}
r12={1d,1u} r13={1d} r14={1d} r15={1d} r16={1d} r17={1d} r42={1d} r43={1d}
r44={1d} r45={1d} r46={1d} r47={1d} r48={1d} r49={1d} r64={1d,1u} r65={1d,2u}
r134={1d,1u} r135={1d,1u} r137={1d,1u}
;; total ref usage 40{25d,15u,0e} in 5{5 regular + 0 call} insns.
( )->[0]->( 2 )
;; bb 0 artificial_defs: { d-1(1){ }d-1(2){ }d-1(8){ }d-1(10){ }d-1(11){
}d-1(12){ }d-1(13){ }d-1(14){ }d-1(15){ }d-1(16){ }d-1(17){ }d-1(42){ }d-1(43){
}d-1(44){ }d-1(45){ }d-1(46){ }d-1(47){ }d-1(48){ }d-1(49){ }d-1(64){ }d-1(65){
}}
;; bb 0 artificial_uses: { }
;; lr in
;; lr use
;; lr def 1 [ra] 2 [sp] 8 [s0] 10 [a0] 11 [a1] 12 [a2] 13 [a3] 14 [a4]
15 [a5] 16 [a6] 17 [a7] 42 [fa0] 43 [fa1] 44 [fa2] 45 [fa3] 46 [fa4] 47 [fa5]
48 [fa6] 49 [fa7] 64 [arg] 65 [frame]
;; live in
;; live gen 1 [ra] 2 [sp] 8 [s0] 10 [a0] 11 [a1] 12 [a2] 13 [a3] 14 [a4]
15 [a5] 16 [a6] 17 [a7] 42 [fa0] 43 [fa1] 44 [fa2] 45 [fa3] 46 [fa4] 47 [fa5]
48 [fa6] 49 [fa7] 64 [arg] 65 [frame]
;; live kill
;; lr out 1 [ra] 2 [sp] 8 [s0] 10 [a0] 12 [a2] 64 [arg] 65 [frame]
;; live out 1 [ra] 2 [sp] 8 [s0] 10 [a0] 12 [a2] 64 [arg] 65 [frame]
( 0 )->[2]->( 1 )
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u-1(2){ }u-1(8){ }u-1(64){ }u-1(65){ }}
;; lr in 1 [ra] 2 [sp] 8 [s0] 10 [a0] 12 [a2] 64 [arg] 65 [frame]
;; lr use 2 [sp] 8 [s0] 10 [a0] 12 [a2] 64 [arg] 65 [frame]
;; lr def 10 [a0] 134 135 137
;; live in 1 [ra] 2 [sp] 8 [s0] 10 [a0] 12 [a2] 64 [arg] 65 [frame]
;; live gen 10 [a0] 134 135 137
;; live kill
;; lr out 1 [ra] 2 [sp] 8 [s0] 10 [a0] 64 [arg] 65 [frame]
;; live out 1 [ra] 2 [sp] 8 [s0] 10 [a0] 64 [arg] 65 [frame]
( 2 )->[1]->( )
;; bb 1 artificial_defs: { }
;; bb 1 artificial_uses: { u-1(1){ }u-1(2){ }u-1(8){ }u-1(10){ }u-1(65){ }}
;; lr in 1 [ra] 2 [sp] 8 [s0] 10 [a0] 65 [frame]
;; lr use 1 [ra] 2 [sp] 8 [s0] 10 [a0] 65 [frame]
;; lr def
;; live in 1 [ra] 2 [sp] 8 [s0] 10 [a0] 65 [frame]
;; live gen
;; live kill
;; lr out
;; live out
Finding needed instructions:
Adding insn 18 to worklist
Finished finding needed instructions:
processing block 2 lr out = 1 [ra] 2 [sp] 8 [s0] 10 [a0] 64 [arg] 65 [frame]
Adding insn 17 to worklist
Adding insn 25 to worklist
Adding insn 4 to worklist
Adding insn 2 to worklist
starting the processing of deferred insns
ending the processing of deferred insns
foo
Dataflow summary:
;; fully invalidated by EH 0 [zero] 1 [ra] 3 [gp] 4 [tp] 5 [t0] 6 [t1] 7
[t2] 10 [a0] 11 [a1] 12 [a2] 13 [a3] 14 [a4] 15 [a5] 16 [a6] 17 [a7] 28 [t3] 29
[t4] 30 [t5] 31 [t6] 32 [ft0] 33 [ft1] 34 [ft2] 35 [ft3] 36 [ft4] 37 [ft5] 38
[ft6] 39 [ft7] 42 [fa0] 43 [fa1] 44 [fa2] 45 [fa3] 46 [fa4] 47 [fa5] 48 [fa6]
49 [fa7] 60 [ft8] 61 [ft9] 62 [ft10] 63 [ft11] 66 [vl] 67 [vtype] 68 [vxrm] 69
[frm] 70 [vxsat] 71 [N/A] 72 [N/A] 73 [N/A] 74 [N/A] 75 [N/A] 76 [N/A] 77 [N/A]
78 [N/A] 79 [N/A] 80 [N/A] 81 [N/A] 82 [N/A] 83 [N/A] 84 [N/A] 85 [N/A] 86
[N/A] 87 [N/A] 88 [N/A] 89 [N/A] 90 [N/A] 91 [N/A] 92 [N/A] 93 [N/A] 94 [N/A]
95 [N/A] 96 [v0] 97 [v1] 98 [v2] 99 [v3] 100 [v4] 101 [v5] 102 [v6] 103 [v7]
104 [v8] 105 [v9] 106 [v10] 107 [v11] 108 [v12] 109 [v13] 110 [v14] 111 [v15]
112 [v16] 113 [v17] 114 [v18] 115 [v19] 116 [v20] 117 [v21] 118 [v22] 119 [v23]
120 [v24] 121 [v25] 122 [v26] 123 [v27] 124 [v28] 125 [v29] 126 [v30] 127 [v31]
;; hardware regs used 2 [sp] 64 [arg] 65 [frame]
;; regular block artificial uses 2 [sp] 8 [s0] 64 [arg] 65 [frame]
;; eh block artificial uses 2 [sp] 8 [s0] 64 [arg] 65 [frame]
;; entry block defs 1 [ra] 2 [sp] 8 [s0] 10 [a0] 11 [a1] 12 [a2] 13 [a3]
14 [a4] 15 [a5] 16 [a6] 17 [a7] 42 [fa0] 43 [fa1] 44 [fa2] 45 [fa3] 46 [fa4] 47
[fa5] 48 [fa6] 49 [fa7] 64 [arg] 65 [frame]
;; exit block uses 1 [ra] 2 [sp] 8 [s0] 10 [a0] 65 [frame]
;; regs ever live 10 [a0] 12 [a2]
;; ref usage r1={1d,1u} r2={1d,2u} r8={1d,2u} r10={2d,3u} r11={1d}
r12={1d,1u} r13={1d} r14={1d} r15={1d} r16={1d} r17={1d} r42={1d} r43={1d}
r44={1d} r45={1d} r46={1d} r47={1d} r48={1d} r49={1d} r64={1d,1u} r65={1d,2u}
r134={1d,1u} r135={1d,1u} r137={1d,1u}
;; total ref usage 40{25d,15u,0e} in 5{5 regular + 0 call} insns.
(note 8 0 2 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn 2 8 4 2 (set (reg/v:DI 135 [ a ])
(reg:DI 10 a0 [ a ]))
"../gcc/testsuite/gcc.target/riscv/pr105314.c":8:1 275 {*movdi_64bit}
(expr_list:REG_DEAD (reg:DI 10 a0 [ a ])
(nil)))
(insn 4 2 5 2 (set (reg/v:DI 137 [ c ])
(reg:DI 12 a2 [ c ]))
"../gcc/testsuite/gcc.target/riscv/pr105314.c":8:1 275 {*movdi_64bit}
(expr_list:REG_DEAD (reg:DI 12 a2 [ c ])
(nil)))
(note 5 4 25 2 NOTE_INSN_FUNCTION_BEG)
(insn 25 5 17 2 (set (reg/v:DI 134 [ <retval> ])
(if_then_else:DI (ne (reg/v:DI 137 [ c ])
(const_int 0 [0]))
(const_int 0 [0])
(reg/v:DI 135 [ a ])))
"../gcc/testsuite/gcc.target/riscv/pr105314.c":9:6 32520 {*czero.nez.didi}
(nil))
(insn 17 25 18 2 (set (reg/i:DI 10 a0)
(reg/v:DI 134 [ <retval> ]))
"../gcc/testsuite/gcc.target/riscv/pr105314.c":12:1 275 {*movdi_64bit}
(expr_list:REG_DEAD (reg/v:DI 134 [ <retval> ])
(nil)))
(insn 18 17 0 2 (use (reg/i:DI 10 a0))
"../gcc/testsuite/gcc.target/riscv/pr105314.c":12:1 -1
(nil))
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1 Due to the optimization of zicond, you will not get "if-conversion succeeded
through noce_try_cmove", but
"if-conversion succeeded through noce_try_store_flag_mask".
2 The same applies to pr105314-rtl.c and pr105314-rtl32.c.
In summary, zicond optimization will cause testcases to fail at point:
"/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through
noce_try_store_flag_mask" 1 "ce1" } } */"
So, it needs to be skipped.
Thanks
Xiao Zeng
