On 7/17/24 3:45 AM, Georg-Johann Lay wrote:
Ping #1 for
https://gcc.gnu.org/pipermail/gcc-patches/2024-July/656332.html
Address computation (usually add) with symbols that are aligned
to 256 bytes does not require to add the lo8() part as it is zero.
This patch adds a new combine insn that performs a widening add
from QImode plus such a symbol. The case when such an aligned
symbol is added to a reg that's already in HImode can be handled
in the addhi3 asm printer.
Ok to apply?
Johann
--
AVR: target90616 - Improve adding constants that are 0 mod 256.
This patch introduces a new insn that works as an insn combine
pattern for (plus:HI (zero_extend:HI(reg:QI) const_0mod256_operannd:HI))
which requires at most 2 instructions. When the input register operand
is already in HImode, the addhi3 printer only adds the hi8 part when
it sees a SYMBOL_REF or CONST aligned to at least 256 bytes.
(The CONST_INT case was already handled).
gcc/
PR target/90616
* config/avr/predicates.md (const_0mod256_operand): New predicate.
* config/avr/constraints.md (Cp8): New constraint.
* config/avr/avr.md (*aligned_add_symbol): New insn.
* config/avr/avr.cc (avr_out_plus_symbol) [HImode]:
When op2 is a multiple of 256, there is no need to add / subtract
the lo8 part.
(avr_rtx_costs_1) [PLUS && HImode]: Return expected costs for
new insn *aligned_add_symbol as it applies.
Sorry. I must have lost this. Thanks for pinging.
It looks fine for the trunk. Out of curiosity, does the avr port
implement linker relaxing for this case? That would seem to be
generally helpful as it'd be able to automatically detect when the
symbolic reference has the right low order bits. Obviously not a
requirement for this patch to go forward, just an observation for
further improvements.
jeff
