Am 16.07.24 um 19:08 schrieb Jeff Law:
On 7/12/24 5:01 AM, Georg-Johann Lay wrote:
These are insns of the forms
(set (regA:M)
(plus:M (extend:M (regB:L))
(regA:M)))
and
(set (regA:M)
(minus:M (regA:M)
(extend:M (regB:L))))
where "extend" may be a sign-extend or zero-extend,
and the integer modes satisfy SImode >= M > L >= QImode.
Currently, these are represented as single insns (and splits).
This patch rewrites them in terms of mode iterators M and L
with SImode >= M > L >= QImode.
This gives 3 new insns (and splits) that cover 6 + 6 + 5 = 17 cases,
where previously there was support for just 8 cases.
The patch handles only the cases that have a plus or a sign-extend.
The minus & zero-extend case was already handled in 077f16b2.
Ok for trunk?
Johann
--
AVR: Overhaul add and sub insns that extend one operand.
These are insns of the forms
(set (regA:M)
(plus:M (extend:M (regB:L))
(regA:M)))
or
(set (regA:M)
(minus:M (regA:M)
(extend:M (regB:L))))
where "extend" may be a sign-extend or zero-extend, and the
integer modes are SImode >= M > L >= QImode.
The existing patterns are now represented in terms of insns
with mode iterators, and these new insn support all valid
combinations of M and L (which previously was not the case).
gcc/
* config/avr/avr.cc (avr_out_minus): Assimilate into...
(avr_out_plus_ext): ...this new function.
(avr_adjust_insn_length) [ADJUST_LEN_PLUS_EXT]: Handle case.
(avr_rtx_costs_1) [PLUS, MINUS]: Adjust RTX costs.
* config/avr/avr.md (adjust_len) <plus_ext>: Add new attribute
value.
(PSISI): New mode iterator.
(*addpsi3_zero_extend.hi_split): Assimilate...
(*addpsi3_zero_extend.qi_split): Assimilate...
(*addsi3_zero_extend_split): Assimilate...
(*addsi3_zero_extend.hi_split): Assimilate...
(*add<PSISI:mode>3.zero_extend.<QIPSI:mode>_split): ...into this
new insn-and-split.
(*addpsi3_zero_extend.hi): Assimilate...
(*addpsi3_zero_extend.qi): Assimilate...
(*addsi3_zero_extend): Assimilate...
(*addsi3_zero_extend.hi): Assimilate...
(*add<PSISI:mode>3.zero_extend.<QIPSI:mode>): ...into this new insn.
(*addpsi3_sign_extend.hi_split): Assimilate...
(*addhi3.sign_extend1_split): Assimilate...
(*add<HISI:mode>3.sign_extend.<QIPSI:mode>_split): ...into this new
insn-and-split.
(*addpsi3_sign_extend.hi): Assimilate...
(*addhi3.sign_extend1): Assimilate...
(*add<HISI:mode>3.sign_extend.<QIPSI:mode>): ...into this new insn.
(*subpsi3_sign_extend.hi_split): Assimilate...
(*subhi3.sign_extend2_split): Assimilate...
(*sub<HISI:mode>3.sign_extend.<QIPSI:mode>_split): ...into this new
insn-and-split.
(*subpsi3_sign_extend.hi): Assimilate...
(*subhi3.sign_extend2): Assimilate...
(*sub<HISI:mode>3.sign_extend.<QIPSI:mode>): ...into this new insn.
(*sub<HISI:mode>3.zero_extend.<QIPSI:mode>): Use avr_out_plus_ext
for asm out.
* config/avr/avr-protos.h (avr_out_minus): Remove.
(avr_out_plus_ext): New proto.
gcc/testsuite/
* gcc.target/avr/torture/add-extend.c: New test.
* gcc.target/avr/torture/sub-extend.c: New test.
OK. A bit hard to follow due to the prior ordering of patterns to make
sure nothing got lost, but I think it all got covered.
Something to consider, I've found having an any_extend code iterator
useful for this kind of pattern consolidation when all that differs is
sign vs zero extend in the pattern.
jeff
Ok, applied with any_extend which already exists:
https://gcc.gnu.org/r15-2068
This shrank the patterns by yet another 50%.
Johann
