Hi,
This patch adds TARGET_FLOAT128_HW into pattern conditions for quad-
precision insns. Also it removes FLOAT128_IEEE_P check from pattern
conditions if the mode of pattern is IEEE128 as the mode iterator -
IEEE128 already checks with FLOAT128_IEEE_P.
For test case float128-cmp2-runnable.c, it should be guarded with
ppc_float128_hw as it calls qp insns. The p9vector_hw is covered with
ppc_float128_hw, so it's removed.
Bootstrapped and tested on powerpc64-linux BE and LE with no
regressions. Is it OK for trunk?
Thanks
Gui Haochen
ChangeLog
rs6000: Add TARGET_FLOAT128_HW guard for quad-precision insns
gcc/
* config/rs6000/rs6000.md (*fpmask<mode>, floatdidf2, floatti<mode>2,
floatunsti<mode>2, fix_trunc<mode>ti2): Add guard
TARGET_FLOAT128_HW.
(add<mode>3, sub<mode>3, mul<mode>3, div<mode>3, sqrt<mode>2,
copysign<mode>3_hard, copysign<mode>3_soft, @neg<mode>2_hw,
@abs<mode>2_hw, *nabs<mode>2_hw, fma<mode>4_hw, *fms<mode>4_hw,
*nfma<mode>4_hw, *nfms<mode>4_hw,
extend<SFDF:mode><IEEE128:mode>2_hw, trunc<mode>df2_hw,
trunc<mode>sf2_hw, fix<uns>_trunc<IEEE128:mode><QHI:mode>2,
*fix<uns>_trunc<IEEE128:mode><QHSI:mode>2_mem,
float_<mode>si2_hw, floatuns_<mode>di2_hw, floor<mode>2,
ceil<mode>2, btrunc<mode>2, round<mode>2, add<mode>3_odd,
sub<mode>3_odd, mul<mode>3_odd, div<mode>3_odd, sqrt<mode>2_odd,
fma<mode>4_odd, *fms<mode>4_odd, *nfma<mode>4_odd,
*nfms<mode>4_odd, trunc<mode>df2_odd, *cmp<mode>_hw for IEEE128):
Remove guard FLOAT128_IEEE_P.
* config/rs6000/vsx.md (xsxexpqp_<IEEE128:mode>_<V2DI_DI:mode>,
xsxsigqp_<IEEE128:mode>_<VEC_TI:mode>, xsiexpqpf_<mode>,
xsiexpqp_<IEEE128:mode>_<V2DI_DI:mode>, xscmpexpqp_<code>_<mode>,
*xscmpexpqp, xststdcnegqp_<mode>): Add guard TARGET_FLOAT128_HW.
(xststdc_<mode>, *xststdc_<mode>, xststdc_<mode>): Add guard
TARGET_FLOAT128_HW for the IEEE128 mode.
gcc/testsuite/
* testsuite/gcc.target/powerpc/float128-cmp2-runnable.c: Replace
ppc_float128_sw with ppc_float128_hw and remove p9vector_hw.
patch.diff
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 3ec5ffa3578..32e5f1c4c56 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5820,7 +5820,7 @@ (define_insn "*fpmask<mode>"
(match_operand:IEEE128 3 "altivec_register_operand" "v")])
(match_operand:V2DI 4 "all_ones_constant" "")
(match_operand:V2DI 5 "zero_constant" "")))]
- "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_POWER10 && TARGET_FLOAT128_HW"
"xscmp%V1qp %0,%2,%3"
[(set_attr "type" "fpcompare")])
@@ -6928,7 +6928,7 @@ (define_insn "floatdidf2"
(define_insn "floatti<mode>2"
[(set (match_operand:IEEE128 0 "vsx_register_operand" "=v")
(float:IEEE128 (match_operand:TI 1 "vsx_register_operand" "v")))]
- "TARGET_POWER10"
+ "TARGET_POWER10 && TARGET_FLOAT128_HW"
{
return "xscvsqqp %0,%1";
}
@@ -6937,7 +6937,7 @@ (define_insn "floatti<mode>2"
(define_insn "floatunsti<mode>2"
[(set (match_operand:IEEE128 0 "vsx_register_operand" "=v")
(unsigned_float:IEEE128 (match_operand:TI 1 "vsx_register_operand"
"v")))]
- "TARGET_POWER10"
+ "TARGET_POWER10 && TARGET_FLOAT128_HW"
{
return "xscvuqqp %0,%1";
}
@@ -6946,7 +6946,7 @@ (define_insn "floatunsti<mode>2"
(define_insn "fix_trunc<mode>ti2"
[(set (match_operand:TI 0 "vsx_register_operand" "=v")
(fix:TI (match_operand:IEEE128 1 "vsx_register_operand" "v")))]
- "TARGET_POWER10"
+ "TARGET_POWER10 && TARGET_FLOAT128_HW"
{
return "xscvqpsqz %0,%1";
}
@@ -6955,7 +6955,7 @@ (define_insn "fix_trunc<mode>ti2"
(define_insn "fixuns_trunc<mode>ti2"
[(set (match_operand:TI 0 "vsx_register_operand" "=v")
(unsigned_fix:TI (match_operand:IEEE128 1 "vsx_register_operand" "v")))]
- "TARGET_POWER10"
+ "TARGET_POWER10 && TARGET_FLOAT128_HW"
{
return "xscvqpuqz %0,%1";
}
@@ -15020,7 +15020,7 @@ (define_insn "add<mode>3"
(plus:IEEE128
(match_operand:IEEE128 1 "altivec_register_operand" "v")
(match_operand:IEEE128 2 "altivec_register_operand" "v")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsaddqp %0,%1,%2"
[(set_attr "type" "vecfloat")
(set_attr "size" "128")])
@@ -15030,7 +15030,7 @@ (define_insn "sub<mode>3"
(minus:IEEE128
(match_operand:IEEE128 1 "altivec_register_operand" "v")
(match_operand:IEEE128 2 "altivec_register_operand" "v")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xssubqp %0,%1,%2"
[(set_attr "type" "vecfloat")
(set_attr "size" "128")])
@@ -15040,7 +15040,7 @@ (define_insn "mul<mode>3"
(mult:IEEE128
(match_operand:IEEE128 1 "altivec_register_operand" "v")
(match_operand:IEEE128 2 "altivec_register_operand" "v")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsmulqp %0,%1,%2"
[(set_attr "type" "qmul")
(set_attr "size" "128")])
@@ -15050,7 +15050,7 @@ (define_insn "div<mode>3"
(div:IEEE128
(match_operand:IEEE128 1 "altivec_register_operand" "v")
(match_operand:IEEE128 2 "altivec_register_operand" "v")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsdivqp %0,%1,%2"
[(set_attr "type" "vecdiv")
(set_attr "size" "128")])
@@ -15059,7 +15059,7 @@ (define_insn "sqrt<mode>2"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(sqrt:IEEE128
(match_operand:IEEE128 1 "altivec_register_operand" "v")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xssqrtqp %0,%1"
[(set_attr "type" "vecdiv")
(set_attr "size" "128")])
@@ -15102,7 +15102,7 @@ (define_insn "copysign<mode>3_hard"
(copysign:IEEE128
(match_operand:IEEE128 1 "altivec_register_operand" "v")
(match_operand:IEEE128 2 "altivec_register_operand" "v")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xscpsgnqp %0,%2,%1"
[(set_attr "type" "vecmove")
(set_attr "size" "128")])
@@ -15113,7 +15113,7 @@ (define_insn "copysign<mode>3_soft"
(match_operand:IEEE128 1 "altivec_register_operand" "v")
(match_operand:IEEE128 2 "altivec_register_operand" "v")))
(clobber (match_scratch:IEEE128 3 "=&v"))]
- "!TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "!TARGET_FLOAT128_HW"
"xscpsgndp %x3,%x2,%x1\;xxpermdi %x0,%x3,%x1,1"
[(set_attr "type" "veccomplex")
(set_attr "length" "8")])
@@ -15122,7 +15122,7 @@ (define_insn "@neg<mode>2_hw"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(neg:IEEE128
(match_operand:IEEE128 1 "altivec_register_operand" "v")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsnegqp %0,%1"
[(set_attr "type" "vecmove")
(set_attr "size" "128")])
@@ -15132,7 +15132,7 @@ (define_insn "@abs<mode>2_hw"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(abs:IEEE128
(match_operand:IEEE128 1 "altivec_register_operand" "v")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsabsqp %0,%1"
[(set_attr "type" "vecmove")
(set_attr "size" "128")])
@@ -15143,7 +15143,7 @@ (define_insn "*nabs<mode>2_hw"
(neg:IEEE128
(abs:IEEE128
(match_operand:IEEE128 1 "altivec_register_operand" "v"))))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsnabsqp %0,%1"
[(set_attr "type" "vecmove")
(set_attr "size" "128")])
@@ -15155,7 +15155,7 @@ (define_insn "fma<mode>4_hw"
(match_operand:IEEE128 1 "altivec_register_operand" "%v")
(match_operand:IEEE128 2 "altivec_register_operand" "v")
(match_operand:IEEE128 3 "altivec_register_operand" "0")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsmaddqp %0,%1,%2"
[(set_attr "type" "qmul")
(set_attr "size" "128")])
@@ -15167,7 +15167,7 @@ (define_insn "*fms<mode>4_hw"
(match_operand:IEEE128 2 "altivec_register_operand" "v")
(neg:IEEE128
(match_operand:IEEE128 3 "altivec_register_operand" "0"))))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsmsubqp %0,%1,%2"
[(set_attr "type" "qmul")
(set_attr "size" "128")])
@@ -15179,7 +15179,7 @@ (define_insn "*nfma<mode>4_hw"
(match_operand:IEEE128 1 "altivec_register_operand" "%v")
(match_operand:IEEE128 2 "altivec_register_operand" "v")
(match_operand:IEEE128 3 "altivec_register_operand" "0"))))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsnmaddqp %0,%1,%2"
[(set_attr "type" "qmul")
(set_attr "size" "128")])
@@ -15192,7 +15192,7 @@ (define_insn "*nfms<mode>4_hw"
(match_operand:IEEE128 2 "altivec_register_operand" "v")
(neg:IEEE128
(match_operand:IEEE128 3 "altivec_register_operand" "0")))))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsnmsubqp %0,%1,%2"
[(set_attr "type" "qmul")
(set_attr "size" "128")])
@@ -15201,7 +15201,7 @@ (define_insn "extend<SFDF:mode><IEEE128:mode>2_hw"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(float_extend:IEEE128
(match_operand:SFDF 1 "altivec_register_operand" "v")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xscvdpqp %0,%1"
[(set_attr "type" "vecfloat")
(set_attr "size" "128")])
@@ -15244,7 +15244,7 @@ (define_insn "trunc<mode>df2_hw"
[(set (match_operand:DF 0 "altivec_register_operand" "=v")
(float_truncate:DF
(match_operand:IEEE128 1 "altivec_register_operand" "v")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xscvqpdp %0,%1"
[(set_attr "type" "vecfloat")
(set_attr "size" "128")])
@@ -15287,7 +15287,7 @@ (define_insn_and_split "trunc<mode>sf2_hw"
(define_insn "fix<uns>_<IEEE128:mode><SDI:mode>2_hw"
[(set (match_operand:SDI 0 "altivec_register_operand" "=v")
(any_fix:SDI (match_operand:IEEE128 1 "altivec_register_operand" "v")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xscvqp<su><wd>z %0,%1"
[(set_attr "type" "vecfloat")
(set_attr "size" "128")])
@@ -15296,7 +15296,7 @@ (define_insn "fix<uns>_trunc<IEEE128:mode><QHI:mode>2"
[(set (match_operand:QHI 0 "altivec_register_operand" "=v")
(any_fix:QHI
(match_operand:IEEE128 1 "altivec_register_operand" "v")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xscvqp<su>wz %0,%1"
[(set_attr "type" "vecfloat")
(set_attr "size" "128")])
@@ -15319,7 +15319,7 @@ (define_insn_and_split
"*fix<uns>_trunc<IEEE128:mode><QHSI:mode>2_mem"
(define_insn "float_<mode>di2_hw"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(float:IEEE128 (match_operand:DI 1 "altivec_register_operand" "v")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xscvsdqp %0,%1"
[(set_attr "type" "vecfloat")
(set_attr "size" "128")])
@@ -15328,7 +15328,7 @@ (define_insn_and_split "float_<mode>si2_hw"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(float:IEEE128 (match_operand:SI 1 "nonimmediate_operand" "vrZ")))
(clobber (match_scratch:DI 2 "=v"))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"#"
"&& 1"
[(set (match_dup 2)
@@ -15384,7 +15384,7 @@ (define_insn "floatuns_<mode>di2_hw"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unsigned_float:IEEE128
(match_operand:DI 1 "altivec_register_operand" "v")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xscvudqp %0,%1"
[(set_attr "type" "vecfloat")
(set_attr "size" "128")])
@@ -15447,7 +15447,7 @@ (define_insn "floor<mode>2"
(unspec:IEEE128
[(match_operand:IEEE128 1 "altivec_register_operand" "v")]
UNSPEC_FRIM))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsrqpi 1,%0,%1,3"
[(set_attr "type" "vecfloat")
(set_attr "size" "128")])
@@ -15457,7 +15457,7 @@ (define_insn "ceil<mode>2"
(unspec:IEEE128
[(match_operand:IEEE128 1 "altivec_register_operand" "v")]
UNSPEC_FRIP))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsrqpi 1,%0,%1,2"
[(set_attr "type" "vecfloat")
(set_attr "size" "128")])
@@ -15467,7 +15467,7 @@ (define_insn "btrunc<mode>2"
(unspec:IEEE128
[(match_operand:IEEE128 1 "altivec_register_operand" "v")]
UNSPEC_FRIZ))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsrqpi 1,%0,%1,1"
[(set_attr "type" "vecfloat")
(set_attr "size" "128")])
@@ -15477,7 +15477,7 @@ (define_insn "round<mode>2"
(unspec:IEEE128
[(match_operand:IEEE128 1 "altivec_register_operand" "v")]
UNSPEC_FRIN))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsrqpi 0,%0,%1,0"
[(set_attr "type" "vecfloat")
(set_attr "size" "128")])
@@ -15489,7 +15489,7 @@ (define_insn "add<mode>3_odd"
[(match_operand:IEEE128 1 "altivec_register_operand" "v")
(match_operand:IEEE128 2 "altivec_register_operand" "v")]
UNSPEC_ADD_ROUND_TO_ODD))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsaddqpo %0,%1,%2"
[(set_attr "type" "vecfloat")
(set_attr "size" "128")])
@@ -15500,7 +15500,7 @@ (define_insn "sub<mode>3_odd"
[(match_operand:IEEE128 1 "altivec_register_operand" "v")
(match_operand:IEEE128 2 "altivec_register_operand" "v")]
UNSPEC_SUB_ROUND_TO_ODD))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xssubqpo %0,%1,%2"
[(set_attr "type" "vecfloat")
(set_attr "size" "128")])
@@ -15511,7 +15511,7 @@ (define_insn "mul<mode>3_odd"
[(match_operand:IEEE128 1 "altivec_register_operand" "v")
(match_operand:IEEE128 2 "altivec_register_operand" "v")]
UNSPEC_MUL_ROUND_TO_ODD))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsmulqpo %0,%1,%2"
[(set_attr "type" "qmul")
(set_attr "size" "128")])
@@ -15522,7 +15522,7 @@ (define_insn "div<mode>3_odd"
[(match_operand:IEEE128 1 "altivec_register_operand" "v")
(match_operand:IEEE128 2 "altivec_register_operand" "v")]
UNSPEC_DIV_ROUND_TO_ODD))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsdivqpo %0,%1,%2"
[(set_attr "type" "vecdiv")
(set_attr "size" "128")])
@@ -15532,7 +15532,7 @@ (define_insn "sqrt<mode>2_odd"
(unspec:IEEE128
[(match_operand:IEEE128 1 "altivec_register_operand" "v")]
UNSPEC_SQRT_ROUND_TO_ODD))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xssqrtqpo %0,%1"
[(set_attr "type" "vecdiv")
(set_attr "size" "128")])
@@ -15544,7 +15544,7 @@ (define_insn "fma<mode>4_odd"
(match_operand:IEEE128 2 "altivec_register_operand" "v")
(match_operand:IEEE128 3 "altivec_register_operand" "0")]
UNSPEC_FMA_ROUND_TO_ODD))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsmaddqpo %0,%1,%2"
[(set_attr "type" "qmul")
(set_attr "size" "128")])
@@ -15557,7 +15557,7 @@ (define_insn "*fms<mode>4_odd"
(neg:IEEE128
(match_operand:IEEE128 3 "altivec_register_operand" "0"))]
UNSPEC_FMA_ROUND_TO_ODD))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsmsubqpo %0,%1,%2"
[(set_attr "type" "qmul")
(set_attr "size" "128")])
@@ -15570,7 +15570,7 @@ (define_insn "*nfma<mode>4_odd"
(match_operand:IEEE128 2 "altivec_register_operand" "v")
(match_operand:IEEE128 3 "altivec_register_operand" "0")]
UNSPEC_FMA_ROUND_TO_ODD)))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsnmaddqpo %0,%1,%2"
[(set_attr "type" "qmul")
(set_attr "size" "128")])
@@ -15584,7 +15584,7 @@ (define_insn "*nfms<mode>4_odd"
(neg:IEEE128
(match_operand:IEEE128 3 "altivec_register_operand" "0"))]
UNSPEC_FMA_ROUND_TO_ODD)))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsnmsubqpo %0,%1,%2"
[(set_attr "type" "qmul")
(set_attr "size" "128")])
@@ -15593,7 +15593,7 @@ (define_insn "trunc<mode>df2_odd"
[(set (match_operand:DF 0 "vsx_register_operand" "=v")
(unspec:DF [(match_operand:IEEE128 1 "altivec_register_operand" "v")]
UNSPEC_TRUNC_ROUND_TO_ODD))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xscvqpdpo %0,%1"
[(set_attr "type" "vecfloat")
(set_attr "size" "128")])
@@ -15603,7 +15603,7 @@ (define_insn "*cmp<mode>_hw"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(compare:CCFP (match_operand:IEEE128 1 "altivec_register_operand" "v")
(match_operand:IEEE128 2 "altivec_register_operand"
"v")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xscmpuqp %0,%1,%2"
[(set_attr "type" "veccmp")
(set_attr "size" "128")])
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 56d1d8c737e..b5c143b1523 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -5157,7 +5157,7 @@ (define_insn "xsxexpqp_<IEEE128:mode>_<V2DI_DI:mode>"
(unspec:V2DI_DI
[(match_operand:IEEE128 1 "altivec_register_operand" "v")]
UNSPEC_VSX_SXEXPDP))]
- "TARGET_P9_VECTOR"
+ "TARGET_P9_VECTOR && TARGET_FLOAT128_HW"
"xsxexpqp %0,%1"
[(set_attr "type" "vecmove")])
@@ -5176,7 +5176,7 @@ (define_insn "xsxsigqp_<IEEE128:mode>_<VEC_TI:mode>"
(unspec:VEC_TI [(match_operand:IEEE128 1
"altivec_register_operand" "v")]
UNSPEC_VSX_SXSIG))]
- "TARGET_P9_VECTOR"
+ "TARGET_P9_VECTOR && TARGET_FLOAT128_HW"
"xsxsigqp %0,%1"
[(set_attr "type" "vecmove")])
@@ -5196,7 +5196,7 @@ (define_insn "xsiexpqpf_<mode>"
[(match_operand:IEEE128 1 "altivec_register_operand" "v")
(match_operand:DI 2 "altivec_register_operand" "v")]
UNSPEC_VSX_SIEXPQP))]
- "TARGET_P9_VECTOR"
+ "TARGET_P9_VECTOR && TARGET_FLOAT128_HW"
"xsiexpqp %0,%1,%2"
[(set_attr "type" "vecmove")])
@@ -5208,7 +5208,7 @@ (define_insn "xsiexpqp_<IEEE128:mode>_<V2DI_DI:mode>"
(match_operand:V2DI_DI 2
"altivec_register_operand" "v")]
UNSPEC_VSX_SIEXPQP))]
- "TARGET_P9_VECTOR"
+ "TARGET_P9_VECTOR && TARGET_FLOAT128_HW"
"xsiexpqp %0,%1,%2"
[(set_attr "type" "vecmove")])
@@ -5278,7 +5278,7 @@ (define_expand "xscmpexpqp_<code>_<mode>"
(set (match_operand:SI 0 "register_operand" "=r")
(CMP_TEST:SI (match_dup 3)
(const_int 0)))]
- "TARGET_P9_VECTOR"
+ "TARGET_P9_VECTOR && TARGET_FLOAT128_HW"
{
if (<CODE> == UNORDERED && !HONOR_NANS (<MODE>mode))
{
@@ -5296,7 +5296,7 @@ (define_insn "*xscmpexpqp"
(match_operand:IEEE128 2 "altivec_register_operand"
"v")]
UNSPEC_VSX_SCMPEXPQP)
(match_operand:SI 3 "zero_constant" "j")))]
- "TARGET_P9_VECTOR"
+ "TARGET_P9_VECTOR && TARGET_FLOAT128_HW"
"xscmpexpqp %0,%1,%2"
[(set_attr "type" "fpcompare")])
@@ -5315,7 +5315,8 @@ (define_expand "xststdc_<mode>"
(set (match_operand:SI 0 "register_operand" "=r")
(eq:SI (match_dup 3)
(const_int 0)))]
- "TARGET_P9_VECTOR"
+ "TARGET_P9_VECTOR
+ && (!FLOAT128_IEEE_P (<MODE>mode) || TARGET_FLOAT128_HW)"
{
operands[3] = gen_reg_rtx (CCFPmode);
operands[4] = CONST0_RTX (SImode);
@@ -5324,7 +5325,9 @@ (define_expand "xststdc_<mode>"
(define_expand "isinf<mode>2"
[(use (match_operand:SI 0 "gpc_reg_operand"))
(use (match_operand:IEEE_FP 1 "<vsx_altivec>"))]
- "TARGET_HARD_FLOAT && TARGET_P9_VECTOR"
+ "TARGET_P9_VECTOR
+ && ((!FLOAT128_IEEE_P (<MODE>mode) && TARGET_HARD_FLOAT)
+ || (FLOAT128_IEEE_P (<MODE>mode) && TARGET_FLOAT128_HW))"
{
int mask = VSX_TEST_DATA_CLASS_POS_INF | VSX_TEST_DATA_CLASS_NEG_INF;
emit_insn (gen_xststdc_<mode> (operands[0], operands[1], GEN_INT (mask)));
@@ -5343,7 +5346,7 @@ (define_expand "xststdcnegqp_<mode>"
(set (match_operand:SI 0 "register_operand" "=r")
(lt:SI (match_dup 2)
(const_int 0)))]
- "TARGET_P9_VECTOR"
+ "TARGET_P9_VECTOR && TARGET_FLOAT128_HW"
{
operands[2] = gen_reg_rtx (CCFPmode);
})
@@ -5374,7 +5377,8 @@ (define_insn "*xststdc_<mode>"
(match_operand:SI 2 "u7bit_cint_operand" "n")]
UNSPEC_VSX_STSTDC)
(const_int 0)))]
- "TARGET_P9_VECTOR"
+ "TARGET_P9_VECTOR
+ && (!FLOAT128_IEEE_P (<MODE>mode) || TARGET_FLOAT128_HW)"
"xststdc<sdq>p %0,%<x>1,%2"
[(set_attr "type" "fpcompare")])
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-cmp2-runnable.c
b/gcc/testsuite/gcc.target/powerpc/float128-cmp2-runnable.c
index d376a3ca68e..f48aa089b05 100644
--- a/gcc/testsuite/gcc.target/powerpc/float128-cmp2-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/float128-cmp2-runnable.c
@@ -1,6 +1,5 @@
/* { dg-do run } */
-/* { dg-require-effective-target ppc_float128_sw } */
-/* { dg-require-effective-target p9vector_hw } */
+/* { dg-require-effective-target ppc_float128_hw } */
/* { dg-options "-O2 -mdejagnu-cpu=power9 " } */
#define NAN_Q __builtin_nanq ("")
