Andrew Pinski <quic_apin...@quicinc.com> writes:
> Bitreverse rtl code was added with r14-1586-g6160572f8d243c. So let's
> use it instead of an unspec. This is just a small cleanup but it does
> have one small fix with respect to rtx costs which didn't handle vector modes
> correctly for the UNSPEC and now it does.
> This is part of the first step in adding __builtin_bitreverse's builtins
> but it is independent of it though.
Nice cleanup.
> Bootstrapped and tested on aarch64-linux-gnu with no regressions.
>
> gcc/ChangeLog:
>
> PR target/115176
> * config/aarch64/aarch64-simd.md (aarch64_rbit<mode><vczle><vczbe>): Use
> bitreverse instead of unspec.
> * config/aarch64/aarch64-sve-builtins-base.cc (svrbit): Convert over to
> using
> rtx_code_function instead of unspec_based_function.
> * config/aarch64/aarch64-sve.md: Update comment where RBIT is included.
> * config/aarch64/aarch64.cc (aarch64_rtx_costs): Handle BITREVERSE like
> BSWAP.
> Remove UNSPEC_RBIT support.
> * config/aarch64/aarch64.md (unspec): Remove UNSPEC_RBIT.
> (aarch64_rbit<mode>): Use bitreverse instead of unspec.
> * config/aarch64/iterators.md (SVE_INT_UNARY): Add bitreverse.
> (optab): Likewise.
> (sve_int_op): Likewise.
> (SVE_INT_UNARY): Remove UNSPEC_RBIT.
> (optab): Likewise.
> (sve_int_op): Likewise.
> (min_elem_bits): Likewise.
>
> Signed-off-by: Andrew Pinski <quic_apin...@quicinc.com>
> ---
> gcc/config/aarch64/aarch64-simd.md | 3 +--
> gcc/config/aarch64/aarch64-sve-builtins-base.cc | 2 +-
> gcc/config/aarch64/aarch64-sve.md | 2 +-
> gcc/config/aarch64/aarch64.cc | 10 ++--------
> gcc/config/aarch64/aarch64.md | 3 +--
> gcc/config/aarch64/iterators.md | 10 +++++-----
> 6 files changed, 11 insertions(+), 19 deletions(-)
>
> diff --git a/gcc/config/aarch64/aarch64-simd.md
> b/gcc/config/aarch64/aarch64-simd.md
> index f644bd1731e..0bb39091a38 100644
> --- a/gcc/config/aarch64/aarch64-simd.md
> +++ b/gcc/config/aarch64/aarch64-simd.md
> @@ -377,8 +377,7 @@ (define_insn "bswap<mode>2"
>
> (define_insn "aarch64_rbit<mode><vczle><vczbe>"
> [(set (match_operand:VB 0 "register_operand" "=w")
> - (unspec:VB [(match_operand:VB 1 "register_operand" "w")]
> - UNSPEC_RBIT))]
> + (bitreverse:VB (match_operand:VB 1 "register_operand" "w")))]
> "TARGET_SIMD"
> "rbit\\t%0.<Vbtype>, %1.<Vbtype>"
> [(set_attr "type" "neon_rbit")]
> diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
> b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
> index 0d2edf3f19e..dea2f6e6bfc 100644
> --- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
> +++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
> @@ -3186,7 +3186,7 @@ FUNCTION (svqincp, svqdecp_svqincp_impl, (SS_PLUS,
> US_PLUS))
> FUNCTION (svqincw, svqinc_bhwd_impl, (SImode))
> FUNCTION (svqincw_pat, svqinc_bhwd_impl, (SImode))
> FUNCTION (svqsub, rtx_code_function, (SS_MINUS, US_MINUS, -1))
> -FUNCTION (svrbit, unspec_based_function, (UNSPEC_RBIT, UNSPEC_RBIT, -1))
> +FUNCTION (svrbit, rtx_code_function, (BITREVERSE, BITREVERSE, -1))
> FUNCTION (svrdffr, svrdffr_impl,)
> FUNCTION (svrecpe, unspec_based_function, (-1, UNSPEC_URECPE, UNSPEC_FRECPE))
> FUNCTION (svrecps, unspec_based_function, (-1, -1, UNSPEC_FRECPS))
> diff --git a/gcc/config/aarch64/aarch64-sve.md
> b/gcc/config/aarch64/aarch64-sve.md
> index d69db34016a..5331e7121d5 100644
> --- a/gcc/config/aarch64/aarch64-sve.md
> +++ b/gcc/config/aarch64/aarch64-sve.md
> @@ -3083,6 +3083,7 @@ (define_expand "vec_extract<vpred><Vel>"
> ;; - CLS (= clrsb)
> ;; - CLZ
> ;; - CNT (= popcount)
> +;; - RBIT (= bitreverse)
> ;; - NEG
> ;; - NOT
> ;; -------------------------------------------------------------------------
> @@ -3171,7 +3172,6 @@ (define_insn "*cond_<optab><mode>_any"
> ;; ---- [INT] General unary arithmetic corresponding to unspecs
> ;; -------------------------------------------------------------------------
> ;; Includes
> -;; - RBIT
> ;; - REVB
> ;; - REVH
> ;; - REVW
> diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
> index 13191ec8e34..0e9d7b1ec0f 100644
> --- a/gcc/config/aarch64/aarch64.cc
> +++ b/gcc/config/aarch64/aarch64.cc
> @@ -14690,6 +14690,7 @@ cost_plus:
> return true;
> }
>
> + case BITREVERSE:
> case BSWAP:
> *cost = COSTS_N_INSNS (1);
>
> @@ -15339,16 +15340,9 @@ cost_plus:
>
> return false;
> }
> -
> - if (XINT (x, 1) == UNSPEC_RBIT)
> - {
> - if (speed)
> - *cost += extra_cost->alu.rev;
> -
> - return false;
> - }
> break;
>
> +
The extra blank line here seems unnecessary.
OK otherwise, thanks.
Richard
> case TRUNCATE:
>
> /* Decompose <su>muldi3_highpart. */
> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
> index dd88fd891b5..69167ab0c04 100644
> --- a/gcc/config/aarch64/aarch64.md
> +++ b/gcc/config/aarch64/aarch64.md
> @@ -259,7 +259,6 @@ (define_c_enum "unspec" [
> UNSPEC_PACIBSP
> UNSPEC_PRLG_STK
> UNSPEC_REV
> - UNSPEC_RBIT
> UNSPEC_SADALP
> UNSPEC_SCVTF
> UNSPEC_SETMEM
> @@ -5406,7 +5405,7 @@ (define_insn "clrsb<mode>2"
>
> (define_insn "@aarch64_rbit<mode>"
> [(set (match_operand:GPI 0 "register_operand" "=r")
> - (unspec:GPI [(match_operand:GPI 1 "register_operand" "r")]
> UNSPEC_RBIT))]
> + (bitreverse:GPI (match_operand:GPI 1 "register_operand" "r")))]
> ""
> "rbit\\t%<w>0, %<w>1"
> [(set_attr "type" "rbit")]
> diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
> index 99cde46f1ba..f527b2cfeb8 100644
> --- a/gcc/config/aarch64/iterators.md
> +++ b/gcc/config/aarch64/iterators.md
> @@ -2525,6 +2525,7 @@ (define_code_iterator ALL_TRUNC [ss_truncate
> us_truncate truncate])
>
> ;; SVE integer unary operations.
> (define_code_iterator SVE_INT_UNARY [abs neg not clrsb clz popcount
> + bitreverse
> (ss_abs "TARGET_SVE2")
> (ss_neg "TARGET_SVE2")])
>
> @@ -2573,6 +2574,7 @@ (define_code_attr optab [(ashift "ashl")
> (clrsb "clrsb")
> (clz "clz")
> (popcount "popcount")
> + (bitreverse "rbit")
> (and "and")
> (ior "ior")
> (xor "xor")
> @@ -2785,6 +2787,7 @@ (define_code_attr sve_int_op [(plus "add")
> (clrsb "cls")
> (clz "clz")
> (popcount "cnt")
> + (bitreverse "rbit")
> (ss_plus "sqadd")
> (us_plus "uqadd")
> (ss_minus "sqsub")
> @@ -2990,7 +2993,7 @@ (define_int_iterator CLAST [UNSPEC_CLASTA
> UNSPEC_CLASTB])
>
> (define_int_iterator LAST [UNSPEC_LASTA UNSPEC_LASTB])
>
> -(define_int_iterator SVE_INT_UNARY [UNSPEC_RBIT UNSPEC_REVB
> +(define_int_iterator SVE_INT_UNARY [UNSPEC_REVB
> UNSPEC_REVH UNSPEC_REVW])
>
> (define_int_iterator SVE_FP_UNARY [UNSPEC_FRECPE UNSPEC_RSQRTE])
> @@ -3568,7 +3571,6 @@ (define_int_attr optab [(UNSPEC_ANDF "and")
> (UNSPEC_FRECPS "frecps")
> (UNSPEC_RSQRTE "frsqrte")
> (UNSPEC_RSQRTS "frsqrts")
> - (UNSPEC_RBIT "rbit")
> (UNSPEC_REVB "revb")
> (UNSPEC_REVD "revd")
> (UNSPEC_REVH "revh")
> @@ -4039,7 +4041,6 @@ (define_int_attr sve_int_op [(UNSPEC_ADCLB "adclb")
> (UNSPEC_PMULLT_PAIR "pmullt")
> (UNSPEC_RADDHNB "raddhnb")
> (UNSPEC_RADDHNT "raddhnt")
> - (UNSPEC_RBIT "rbit")
> (UNSPEC_REVB "revb")
> (UNSPEC_REVH "revh")
> (UNSPEC_REVW "revw")
> @@ -4416,8 +4417,7 @@ (define_int_attr max_elem_bits [(UNSPEC_UADDV "64")
> (UNSPEC_SADDV "32")
> (UNSPEC_PFIRST "8") (UNSPEC_PNEXT "64")])
>
> ;; The minimum number of element bits that an instruction can handle.
> -(define_int_attr min_elem_bits [(UNSPEC_RBIT "8")
> - (UNSPEC_REVB "16")
> +(define_int_attr min_elem_bits [(UNSPEC_REVB "16")
> (UNSPEC_REVH "32")
> (UNSPEC_REVW "64")])
