On 6/3/24 3:53 PM, Patrick O'Neill wrote:
All amo<op> patterns can be represented with lrsc sequences.
Add these patterns as a fallback when Zaamo is not enabled.
gcc/ChangeLog:
* config/riscv/sync.md (atomic_<atomic_optab><mode>): New expand
pattern.
(amo_atomic_<atomic_optab><mode>): Rename amo pattern.
(atomic_fetch_<atomic_optab><mode>): New lrsc sequence pattern.
(lrsc_atomic_<atomic_optab><mode>): New expand pattern.
(amo_atomic_fetch_<atomic_optab><mode>): Rename amo pattern.
(lrsc_atomic_fetch_<atomic_optab><mode>): New lrsc sequence pattern.
(atomic_exchange<mode>): New expand pattern.
(amo_atomic_exchange<mode>): Rename amo pattern.
(lrsc_atomic_exchange<mode>): New lrsc sequence pattern.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c: New test.
* gcc.target/riscv/amo-zalrsc-amo-add-1.c: New test.
* gcc.target/riscv/amo-zalrsc-amo-add-2.c: New test.
* gcc.target/riscv/amo-zalrsc-amo-add-3.c: New test.
* gcc.target/riscv/amo-zalrsc-amo-add-4.c: New test.
* gcc.target/riscv/amo-zalrsc-amo-add-5.c: New test.
Signed-off-by: Patrick O'Neill <patr...@rivosinc.com>
------
rv64imfdc_zalrsc has the same testsuite results as rv64imafdc after this
patch is applied.
---
AFAIK there isn't a way to subtract an extension similar to dg-add-options.
As a result I needed to specify a -march string for
amo-zaamo-preferred-over-zalrsc.c instead of using testsuite infra.
I believe you are correct.
diff --git a/gcc/testsuite/gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c
b/gcc/testsuite/gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c
new file mode 100644
index 00000000000..1c124c2b8b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c
[ ... ]
Not a big fan of the function-bodies tests. If we're going to use them,
we need to be especially careful about requiring specific registers so
that we're not stuck adjusting them all the time due to changes in the
regsiter allocator, optimizers, etc.
diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-1.c
b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-1.c
new file mode 100644
index 00000000000..3cd6ce04830
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping.
*/
+/* { dg-options "-O3 -march=rv64id_zalrsc" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** foo:
+** 1:
+** lr.w\ta5, 0\(a0\)
+** add\ta5, a5, a1
+** sc.w\ta5, a5, 0\(a0\)
+** bnez\ta5, 1b
+** ret
+*/
+void foo (int* bar, int* baz)
+{
+ __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED);
+}
This one is a good example. We could just as easily use a variety of
registers other than a5 for the temporary.
Obviously for registers that hold the incoming argument or an outgoing
result, we can be more strict.
If you could take a look at the added tests and generalize the registers
it'd be appreciated. OK with that adjustment.
jeff
