Hi Martin, On Thu, 2 May 2024, Martin Jambor wrote: > + <li> GCC now supports AMD CPUs based on the znver5 core via > + <code>-march=znver5</code>. Based on ISA extensions enabled on > + a znver4 core, the switch further enables the AVXVNNI, MOVDIRI, > + MOVDIR64B, AVX512VP2INTERSECT, and PREFETCHI ISA extensions.
just two small suggestions: We usually sort extensions alphabetically, so AVX512VP2INTERSECT, AVXVNNI, MOVDIR64B, MOVDIRI, and PREFETCHI. If there is a specific reason to do otherwise, that's okay of course. And I might write "In addition to the ISA extensions enabled on a znver4 core, this switch..." to avoid the repetition of "based on" (and make it a bit more clear even that it is a full superset, not just 'loosely' based". Gerald
