Don't use implicit shift count in double-precision shifts in AT&T syntax
since they aren't in Intel SDM.  Keep the 's' modifier for backward
compatibility with inline asm statements.

        PR target/114590
        * config/i386/i386.md (x86_64_shld): Use explicit shift count in
        AT&T syntax.
        (x86_64_shld_ndd): Likewise.
        (x86_shld): Likewise.
        (x86_shld_ndd): Likewise.
        (x86_64_shrd): Likewise.
        (x86_64_shrd_ndd): Likewise.
        (x86_shrd): Likewise.
        (x86_shrd_ndd): Likewise.
---
 gcc/config/i386/i386.md | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 6ac401154e4..bb2c72f3473 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -14503,7 +14503,7 @@ (define_insn "x86_64_shld"
                              (and:QI (match_dup 2) (const_int 63)))) 0)))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT"
-  "shld{q}\t{%s2%1, %0|%0, %1, %2}"
+  "shld{q}\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "ishift")
    (set_attr "prefix_0f" "1")
    (set_attr "mode" "DI")
@@ -14524,7 +14524,7 @@ (define_insn "x86_64_shld_ndd"
                              (and:QI (match_dup 3) (const_int 63)))) 0)))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_APX_NDD"
-  "shld{q}\t{%s3%2, %1, %0|%0, %1, %2, %3}"
+  "shld{q}\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ishift")
    (set_attr "mode" "DI")])
 
@@ -14681,7 +14681,7 @@ (define_insn "x86_shld"
                              (and:QI (match_dup 2) (const_int 31)))) 0)))
    (clobber (reg:CC FLAGS_REG))]
   ""
-  "shld{l}\t{%s2%1, %0|%0, %1, %2}"
+  "shld{l}\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "ishift")
    (set_attr "prefix_0f" "1")
    (set_attr "mode" "SI")
@@ -14703,7 +14703,7 @@ (define_insn "x86_shld_ndd"
                              (and:QI (match_dup 3) (const_int 31)))) 0)))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_APX_NDD"
-  "shld{l}\t{%s3%2, %1, %0|%0, %1, %2, %3}"
+  "shld{l}\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ishift")
    (set_attr "mode" "SI")])
 
@@ -15792,7 +15792,7 @@ (define_insn "x86_64_shrd"
                              (and:QI (match_dup 2) (const_int 63)))) 0)))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT"
-  "shrd{q}\t{%s2%1, %0|%0, %1, %2}"
+  "shrd{q}\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "ishift")
    (set_attr "prefix_0f" "1")
    (set_attr "mode" "DI")
@@ -15813,7 +15813,7 @@ (define_insn "x86_64_shrd_ndd"
                              (and:QI (match_dup 3) (const_int 63)))) 0)))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_APX_NDD"
-  "shrd{q}\t{%s3%2, %1, %0|%0, %1, %2, %3}"
+  "shrd{q}\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ishift")
    (set_attr "mode" "DI")])
 
@@ -15971,7 +15971,7 @@ (define_insn "x86_shrd"
                              (and:QI (match_dup 2) (const_int 31)))) 0)))
    (clobber (reg:CC FLAGS_REG))]
   ""
-  "shrd{l}\t{%s2%1, %0|%0, %1, %2}"
+  "shrd{l}\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "ishift")
    (set_attr "prefix_0f" "1")
    (set_attr "mode" "SI")
@@ -15993,7 +15993,7 @@ (define_insn "x86_shrd_ndd"
                              (and:QI (match_dup 3) (const_int 31)))) 0)))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_APX_NDD"
-  "shrd{l}\t{%s3%2, %1, %0|%0, %1, %2, %3}"
+  "shrd{l}\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ishift")
    (set_attr "mode" "SI")])
 
-- 
2.44.0

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