Re: [PATCH] RISC-V: Refine the condition for add additional vars in RVV cost model

[Jeff Law]

On 3/28/24 4:31 AM, demin.han wrote:
The adjacent_dr_p is sufficient and unnecessary condition for contiguous access.
So unnecessary live-ranges are added and result in spill.

This patch uses MEMORY_ACCESS_TYPE as condition and constrains segment
load/store.

Tested on RV64 and no regression.

        PR target/114506

gcc/ChangeLog:

        * config/riscv/riscv-vector-costs.cc (non_contiguous_memory_access_p): 
Rename
        (need_additional_vector_vars_p): Rename and refine condition

gcc/testsuite/ChangeLog:

        * gcc.dg/vect/costmodel/riscv/rvv/pr114506.c: New test.
Note I think this should defer to gcc-15.  It doesn't affect code 
correctness AFAICT and it's not a regression relative to gcc-13.

jeff