Yeah, that's the plan for the longer term, we would like to build the schedule model first and then run more benchmarks with that, then enable dynamic lmul by default, most SiFive cores prefer larger LMUL if possible/no spill.
On Thu, Feb 1, 2024 at 4:14 PM juzhe.zh...@rivai.ai <juzhe.zh...@rivai.ai> wrote: > > Thanks. I wonder whether p600 will enable dynamic lmul by default ? > Does dynamic LMUL help with sifive p600 chip ? > > ________________________________ > juzhe.zh...@rivai.ai > > > From: Monk Chiang > Date: 2024-02-01 16:10 > To: juzhe.zh...@rivai.ai > CC: gcc-patches; kito.cheng > Subject: Re: [PATCH v2] RISC-V: Support scheduling for sifive p600 series > Hi Juzhe, > The vector part is complicated, I will add it last. > > On Thu, Feb 1, 2024 at 11:08 AM juzhe.zh...@rivai.ai <juzhe.zh...@rivai.ai> > wrote: >> >> Hi, Monk. >> >> This model doesn't include vector. Will you add vector pipeline in the >> followup patches ? >> >> ________________________________ >> juzhe.zh...@rivai.ai
