LGTM with only few comment suggestion
Juzhe-Zhong <juzhe.zh...@rivai.ai>於 2024年1月3日 週三，18:50寫道：
> As PR113206 and PR113209, the bugs happens on the following situation:
>
> li a4,32
> ...
> vsetvli zero,a4,e8,m8,ta,ma
> ...
> slliw a4,a3,24
> sraiw a4,a4,24
> bge a3,a1,.L8
> sb a4,%lo(e)(a0)
> vsetvli zero,a4,e8,m8,ta,ma --> a4 is polluted value not the
> expected "32".
> ...
> .L7:
> j .L7 ---> infinite loop.
>
> The root cause is that infinite loop confuse earliest computation and let
> earliest fusion
> happens on unexpected place.
>
> Disable blocks that belong to infinite loop to fix this bug since applying
> ealiest LCM fusion
> on infinite loop seems quite complicated and we don't see any benefits.
>
> Note that disabling earliest fusion on infinite loops doesn't hurt the
> vsetvli performance,
> instead, it does improve codegen of some cases.
>
> Tested on both RV32 and RV64 no regression.
>
> Ok for trunk ?
>
> PR target/113206
> PR target/113209
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vsetvl.cc (invalid_opt_bb_p): New function.
> (pre_vsetvl::compute_lcm_local_properties): Disable earliest
> fusion on blocks belong to infinite loop.
> (pre_vsetvl::emit_vsetvl): Remove fake edges.
> * config/riscv/t-riscv: Add a new include file.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/vsetvl/avl_single-23.c: Adapt test.
> * gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c: Robostify test.
> * gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c: Ditto.
> * gcc.target/riscv/rvv/autovec/pr113206-1.c: New test.
> * gcc.target/riscv/rvv/autovec/pr113206-2.c: New test.
> * gcc.target/riscv/rvv/autovec/pr113209.c: New test.
>
> ---
> gcc/config/riscv/riscv-vsetvl.cc | 41 +++++++++++++++----
> gcc/config/riscv/t-riscv | 2 +-
> .../gcc.target/riscv/rvv/autovec/pr113206-1.c | 29 +++++++++++++
> .../gcc.target/riscv/rvv/autovec/pr113206-2.c | 29 +++++++++++++
> .../gcc.target/riscv/rvv/autovec/pr113209.c | 34 +++++++++++++++
> .../riscv/rvv/vsetvl/avl_single-23.c | 1 -
> .../riscv/rvv/vsetvl/vlmax_call-1.c | 15 ++++---
> .../riscv/rvv/vsetvl/vlmax_call-2.c | 12 +++---
> .../riscv/rvv/vsetvl/vlmax_call-3.c | 12 +++---
> .../riscv/rvv/vsetvl/vlmax_conflict-5.c | 5 +--
> .../riscv/rvv/vsetvl/vlmax_single_vtype-1.c | 14 +++----
> .../riscv/rvv/vsetvl/vlmax_single_vtype-2.c | 6 +--
> .../riscv/rvv/vsetvl/vlmax_single_vtype-3.c | 6 +--
> .../riscv/rvv/vsetvl/vlmax_single_vtype-4.c | 4 +-
> .../riscv/rvv/vsetvl/vlmax_single_vtype-5.c | 4 +-
> 15 files changed, 164 insertions(+), 50 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113206-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113206-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113209.c
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc
> b/gcc/config/riscv/riscv-vsetvl.cc
> index eabaef80f89..7b1d8376e41 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -85,6 +85,7 @@ along with GCC; see the file COPYING3. If not see
> #include "predict.h"
> #include "profile-count.h"
> #include "gcse.h"
> +#include "cfgloop.h"
>
> using namespace rtl_ssa;
> using namespace riscv_vector;
> @@ -648,6 +649,27 @@ has_no_uses (basic_block cfg_bb, rtx_insn *rinsn, int
> regno)
> return true;
> }
>
> +/* Return true for the special block that we can't apply LCM
> optimization. */
> +static bool
> +invalid_opt_bb_p (basic_block cfg_bb)
> +{
> + edge e;
> + edge_iterator ei;
> +
> + /* We don't do LCM optimizations on complex edges. */
> + FOR_EACH_EDGE (e, ei, cfg_bb->preds)
> + if (e->flags & EDGE_COMPLEX)
> + return true;
> +
> + /* We only do LCM optimizations on blocks that are post dominated by
> + EXIT block, that is, we don't do LCM optimizations on infinite
> loop. */
> + FOR_EACH_EDGE (e, ei, cfg_bb->succs)
> + if (e->flags & EDGE_FAKE)
> + return true;
> +
> + return false;
> +}
> +
> /* This flags indicates the minimum demand of the vl and vtype values by
> the
> RVV instruction. For example, DEMAND_RATIO_P indicates that this RVV
> instruction only needs the SEW/LMUL ratio to remain the same, and does
> not
> @@ -2261,6 +2283,8 @@ public:
> {
> /* Initialization of RTL_SSA. */
> calculate_dominance_info (CDI_DOMINATORS);
> + loop_optimizer_init (LOOPS_NORMAL);
> + connect_infinite_loops_to_exit ();
Add comment to mention it will create edge_fake
> df_analyze ();
> crtl->ssa = new function_info (cfun);
> m_vector_block_infos.safe_grow_cleared (last_basic_block_for_fn
> (cfun));
> @@ -2271,6 +2295,7 @@ public:
> void finish ()
> {
> free_dominance_info (CDI_DOMINATORS);
> + loop_optimizer_finalize ();
> if (crtl->ssa->perform_pending_updates ())
> cleanup_cfg (0);
> delete crtl->ssa;
> @@ -2785,14 +2810,11 @@ pre_vsetvl::compute_lcm_local_properties ()
> for (const bb_info *bb : crtl->ssa->bbs ())
> {
> unsigned bb_index = bb->index ();
> - edge e;
> - edge_iterator ei;
> - FOR_EACH_EDGE (e, ei, bb->cfg_bb ()->preds)
> - if (e->flags & EDGE_COMPLEX)
> - {
> - bitmap_clear (m_antloc[bb_index]);
> - bitmap_clear (m_transp[bb_index]);
> - }
> + if (invalid_opt_bb_p (bb->cfg_bb ()))
> + {
> + bitmap_clear (m_antloc[bb_index]);
> + bitmap_clear (m_transp[bb_index]);
> + }
> }
> }
>
> @@ -3305,6 +3327,9 @@ pre_vsetvl::emit_vsetvl ()
> {
> bool need_commit = false;
>
> + /* We should commit vsetvl edge after fake edges removes,
> + otherwise, it will cause ICE. */
> + remove_fake_exit_edges ();
Also mention it fake edge is created by connect infinite loops to exit
function.
> for (const bb_info *bb : crtl->ssa->bbs ())
> {
> for (const auto &curr_info : get_block_info (bb).local_infos)
> diff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv
> index 067771e3c97..32de6b851c1 100644
> --- a/gcc/config/riscv/t-riscv
> +++ b/gcc/config/riscv/t-riscv
> @@ -64,7 +64,7 @@ riscv-vsetvl.o: $(srcdir)/config/riscv/riscv-vsetvl.cc \
> $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(RTL_H) $(REGS_H) \
> $(TARGET_H) tree-pass.h df.h rtl-ssa.h cfgcleanup.h insn-config.h \
> insn-attr.h insn-opinit.h tm-constrs.h cfgrtl.h cfganal.h lcm.h \
> - predict.h profile-count.h \
> + predict.h profile-count.h cfgloop.h \
> $(srcdir)/config/riscv/riscv-vsetvl.def
> $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
> $(srcdir)/config/riscv/riscv-vsetvl.cc
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113206-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113206-1.c
> new file mode 100644
> index 00000000000..ef92c6f35d1
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113206-1.c
> @@ -0,0 +1,29 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
> +
> +signed char e;
> +short f = 8;
> +signed d;
> +int(g)(int o, int r) { return o & (o ^ -1) < 0 ? o : o - r; }
> +#pragma pack(1)
> +struct {
> + short h;
> + unsigned : 18;
> + short i;
> + long j;
> + int k;
> + char l;
> + long m;
> + int n;
> +} a, b, s, c, *p = &b, *u = &s, q = {1};
> +void t() {
> + *p = a;
> + for (; e > -7; e = g(e, 8))
> + ;
> + q = *u = c;
> + for (; d - 3; d = 3)
> + ;
> +}
> +
> +/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*32} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli} 2 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113206-2.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113206-2.c
> new file mode 100644
> index 00000000000..cfce88988f7
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113206-2.c
> @@ -0,0 +1,29 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -frename-registers" } */
> +
> +signed char e;
> +short f = 8;
> +signed d;
> +int(g)(int o, int r) { return o & (o ^ -1) < 0 ? o : o - r; }
> +#pragma pack(1)
> +struct {
> + short h;
> + unsigned : 18;
> + short i;
> + long j;
> + int k;
> + char l;
> + long m;
> + int n;
> +} a, b, s, c, *p = &b, *u = &s, q = {1};
> +void t() {
> + *p = a;
> + for (; e > -7; e = g(e, 8))
> + ;
> + q = *u = c;
> + for (; d - 3; d = 3)
> + ;
> +}
> +
> +/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*32} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetvli} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113209.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113209.c
> new file mode 100644
> index 00000000000..081ee369394
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113209.c
> @@ -0,0 +1,34 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3" } */
> +
> +int b, c, d, f, i, a;
> +int e[1] = {0};
> +int *g = e;
> +int *k = e;
> +int *z;
> +long h;
> +int j[5] = {0,0,0,0,0};
> +void n() {
> + if (c) {
> + int **l = &z;
> + *l = e;
> + while (d)
> + ;
> + }
> +}
> +void o() {
> + for (; b < 5; b += a) {
> + n();
> + for (h = 0; h < 5; h++)
> + j[h] = 1;
> + int m = *e != *g;
> + a |= i <= m;
> + f = -12;
> + for (; f; f++)
> + if (*k)
> + break;
> + }
> +}
> +
> +/* { dg-final { scan-assembler-times {vsetvli} 1 } } */
> +/* { dg-final { scan-assembler-times {vsetivli} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c
> index 6f8e71402d8..eacebe323ee 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c
> @@ -29,7 +29,6 @@ void f (int8_t * restrict in, int8_t * restrict out, int
> n, int m, int cond)
>
> /* { dg-final { scan-assembler
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} { target {
> no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
> /* { dg-final { scan-assembler
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu} { target { no-opts
> "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
> -/* { dg-final { scan-assembler-times {vsetvli} 4 { target { { any-opts
> "-O1" } && { no-opts "-g" "-funroll-loops" } } } } } */
> /* { dg-final { scan-assembler-times {vsetvli} 3 { target { { any-opts
> "-Os" "-O2" } && { no-opts "-g" "-funroll-loops" } } } } } */
> /* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,101} 1 { target {
> no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
> /* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,102} 1 { target {
> no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c
> index 1dae7071e13..25fc05c7a96 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c
> @@ -223,17 +223,16 @@ int f7 (int8_t * restrict in, int8_t * restrict out,
> int n)
> }
>
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 5 { target {
> no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vlm\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 5 { target {
> no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vlm\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 5 { target {
> no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vlm\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 5 { target {
> no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vlm\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 5 { target {
> no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vlm\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 5 { target {
> no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vlm\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 5 { target {
> no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+\.L[0-9][0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vlm\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c
> index 1e72f616665..cc4fbba33f0 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c
> @@ -192,16 +192,16 @@ void f6 (int8_t * restrict in, int8_t * restrict
> out, int n)
> }
>
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 5 { target {
> no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 5 { target {
> no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 5 { target {
> no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
>
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 5 { target {
> no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vle16\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 5 { target {
> no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vle16\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
>
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 5 { target {
> no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vle32\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c
> index 62d087de9c7..ebbaafcee19 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c
> @@ -192,16 +192,16 @@ void f6 (int8_t * restrict in, int8_t * restrict
> out, int n)
> }
>
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 5 { target {
> no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 5 { target {
> no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 5 { target {
> no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
>
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 5 { target {
> no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vle16\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 5 { target {
> no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vle16\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
>
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 5 { target {
> no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vle32\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 5 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c
> index 5a3e05e4961..cd94fdae4b4 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c
> @@ -26,7 +26,6 @@ void f (int32_t * restrict in, int32_t * restrict out,
> size_t n, size_t cond, si
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 4 { target {
> no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+\.L[0-9]:+} 1
> { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> -/* { dg-final { scan-assembler-times {vsetvli} 7 { target { no-opts
> "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops"
> no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times {vsetvli} 4 { target { no-opts
> "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops"
> no-opts "-g" } } } } */
>
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c
> index f6ecebeb2e1..adb14e5d23b 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c
> @@ -69,13 +69,13 @@ void foo7 (void * restrict in, void * restrict out,
> int n)
> }
> }
>
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vlm\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vlm\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vlm\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vlm\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vlm\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vlm\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vlm\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
>
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c
> index 39576c17e5d..d3a060f9bcf 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c
> @@ -33,9 +33,9 @@ void foo3 (void * restrict in, void * restrict out, int
> n)
> }
> }
>
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
>
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c
> index f5fb770eac6..bd1d9b24112 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c
> @@ -33,6 +33,6 @@ void foo3 (void * restrict in, void * restrict out, int
> n)
> }
> }
>
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c
> index 63282f4558b..1ef0bf84c59 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c
> @@ -24,8 +24,8 @@ void foo3 (void * restrict in, void * restrict out, int
> n)
> }
> }
>
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vle16\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vle16\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
>
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c
> index d9cdb111956..518c74744b9 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c
> @@ -24,8 +24,8 @@ void foo3 (void * restrict in, void * restrict out, int
> n)
> }
> }
>
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> -/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vle16\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vle16\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)}
> 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
> "-funroll-loops" no-opts "-g" } } } } */
>
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
> "-g" } } } } */
> --
> 2.36.3
>
>
