> index 7d7b952d817..e7d4ad1760c 100644 > --- a/gcc/config/riscv/corev.md > +++ b/gcc/config/riscv/corev.md > @@ -27,6 +27,25 @@ > > ;;CORE-V EVENT LOAD > UNSPECV_CV_ELW > + > + ;;CORE-V BITMANIP > + UNSPEC_CV_BITMANIP_EXTRACT > + UNSPEC_CV_BITMANIP_EXTRACT_INSN > + UNSPEC_CV_BITMANIP_EXTRACTR_INSN > + UNSPEC_CV_BITMANIP_EXTRACTU > + UNSPEC_CV_BITMANIP_EXTRACTU_INSN > + UNSPEC_CV_BITMANIP_EXTRACTUR_INSN > + UNSPEC_CV_BITMANIP_INSERT > + UNSPEC_CV_BITMANIP_INSERT_INSN > + UNSPEC_CV_BITMANIP_INSERTR_INSN
You could reference bfe, sbfx and ubfx instructions in aarch64.md to see how to write the insert and extract bit with RTL code. > + UNSPEC_CV_BITMANIP_BCLR > + UNSPEC_CV_BITMANIP_BCLR_INSN > + UNSPEC_CV_BITMANIP_BCLRR_INSN > + UNSPEC_CV_BITMANIP_BSET > + UNSPEC_CV_BITMANIP_BSET_INSN > + UNSPEC_CV_BITMANIP_BSETR_INSN Just use generic RTL code for bset and bclr is fine, you could reference bitmanip.md > + UNSPEC_CV_BITMANIP_BITREV > + UNSPEC_CV_BITMANIP_FL1 > ]) >
