LGTM
On Tue, Nov 28, 2023 at 9:17 PM Mary Bennett <mary.benn...@embecosm.com> wrote: > > gcc/ChangeLog: > * config/riscv/constraints.md: CVP2 -> CV_alu_pow2. > * config/riscv/corev.md: Likewise. > --- > gcc/config/riscv/constraints.md | 15 ++++++++------- > gcc/config/riscv/corev.md | 4 ++-- > 2 files changed, 10 insertions(+), 9 deletions(-) > > diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md > index 68be4515c04..2711efe68c5 100644 > --- a/gcc/config/riscv/constraints.md > +++ b/gcc/config/riscv/constraints.md > @@ -151,13 +151,6 @@ > (define_register_constraint "zmvr" "(TARGET_ZFA || TARGET_XTHEADFMV) ? > GR_REGS : NO_REGS" > "An integer register for ZFA or XTheadFmv.") > > -;; CORE-V Constraints > -(define_constraint "CVP2" > - "Checking for CORE-V ALU clip if ival plus 1 is a power of 2" > - (and (match_code "const_int") > - (and (match_test "IN_RANGE (ival, 0, 1073741823)") > - (match_test "exact_log2 (ival + 1) != -1")))) > - > ;; Vector constraints. > > (define_register_constraint "vr" "TARGET_VECTOR ? V_REGS : NO_REGS" > @@ -246,3 +239,11 @@ > A MEM with a valid address for th.[l|s]*ur* instructions." > (and (match_code "mem") > (match_test "th_memidx_legitimate_index_p (op, true)"))) > + > +;; CORE-V Constraints > +(define_constraint "CV_alu_pow2" > + "@internal > + Checking for CORE-V ALU clip if ival plus 1 is a power of 2" > + (and (match_code "const_int") > + (and (match_test "IN_RANGE (ival, 0, 1073741823)") > + (match_test "exact_log2 (ival + 1) != -1")))) > diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md > index c7a2ba07bcc..92bf0b5d6a6 100644 > --- a/gcc/config/riscv/corev.md > +++ b/gcc/config/riscv/corev.md > @@ -516,7 +516,7 @@ > (define_insn "riscv_cv_alu_clip" > [(set (match_operand:SI 0 "register_operand" "=r,r") > (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") > - (match_operand:SI 2 "immediate_register_operand" "CVP2,r")] > + (match_operand:SI 2 "immediate_register_operand" > "CV_alu_pow2,r")] > UNSPEC_CV_ALU_CLIP))] > > "TARGET_XCVALU && !TARGET_64BIT" > @@ -529,7 +529,7 @@ > (define_insn "riscv_cv_alu_clipu" > [(set (match_operand:SI 0 "register_operand" "=r,r") > (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") > - (match_operand:SI 2 "immediate_register_operand" "CVP2,r")] > + (match_operand:SI 2 "immediate_register_operand" > "CV_alu_pow2,r")] > UNSPEC_CV_ALU_CLIPU))] > > "TARGET_XCVALU && !TARGET_64BIT" > -- > 2.34.1 >
