Hi! On 2023-11-15T14:10:47+0000, Andrew Stubbs <a...@codesourcery.com> wrote: > * gcc.target/gcn/avgpr-mem-double.c: New test. > * gcc.target/gcn/avgpr-mem-int.c: New test. > * gcc.target/gcn/avgpr-mem-long.c: New test. > * gcc.target/gcn/avgpr-mem-short.c: New test. > * gcc.target/gcn/avgpr-spill-double.c: New test. > * gcc.target/gcn/avgpr-spill-int.c: New test. > * gcc.target/gcn/avgpr-spill-long.c: New test. > * gcc.target/gcn/avgpr-spill-short.c: New test.
> --- /dev/null > +++ b/gcc/testsuite/gcc.target/gcn/avgpr-mem-double.c > @@ -0,0 +1,9 @@ > +/* { dg-do compile } */ > +/* { dg-additional-options "-march=gfx90a -O1" } */ > +/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[068]" } } */ > +[...] Etc. OK to push the attached "GCN: Generally enable the 'gcc.target/gcn/avgpr-[...]' test cases"? Grüße Thomas ----------------- Siemens Electronic Design Automation GmbH; Anschrift: Arnulfstraße 201, 80634 München; Gesellschaft mit beschränkter Haftung; Geschäftsführer: Thomas Heurung, Frank Thürauf; Sitz der Gesellschaft: München; Registergericht München, HRB 106955
>From a21b6768b2267cf831089ea2c950c0d77408b1bf Mon Sep 17 00:00:00 2001 From: Thomas Schwinge <tho...@codesourcery.com> Date: Thu, 16 Nov 2023 23:17:36 +0100 Subject: [PATCH] GCN: Generally enable the 'gcc.target/gcn/avgpr-[...]' test cases ... added in commit ae0d2c240213c5a7f6959c032bfc9f0703cab787 "amdgcn: Add Accelerator VGPR registers". This way, they're correctly tested no matter what '-march=[...]' is used with 'make check'. gcc/testsuite/ * gcc.target/gcn/avgpr-mem-double.c: Remove 'dg-skip-if "incompatible ISA" [...]'. * gcc.target/gcn/avgpr-mem-int.c: Likewise. * gcc.target/gcn/avgpr-mem-long.c: Likewise. * gcc.target/gcn/avgpr-mem-short.c: Likewise. * gcc.target/gcn/avgpr-spill-double.c: Likewise. * gcc.target/gcn/avgpr-spill-int.c: Likewise. * gcc.target/gcn/avgpr-spill-long.c: Likewise. * gcc.target/gcn/avgpr-spill-short.c: Likewise. --- gcc/testsuite/gcc.target/gcn/avgpr-mem-double.c | 1 - gcc/testsuite/gcc.target/gcn/avgpr-mem-int.c | 1 - gcc/testsuite/gcc.target/gcn/avgpr-mem-long.c | 1 - gcc/testsuite/gcc.target/gcn/avgpr-mem-short.c | 1 - gcc/testsuite/gcc.target/gcn/avgpr-spill-double.c | 1 - gcc/testsuite/gcc.target/gcn/avgpr-spill-int.c | 1 - gcc/testsuite/gcc.target/gcn/avgpr-spill-long.c | 1 - gcc/testsuite/gcc.target/gcn/avgpr-spill-short.c | 1 - 8 files changed, 8 deletions(-) diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-mem-double.c b/gcc/testsuite/gcc.target/gcn/avgpr-mem-double.c index ce089fb198d..34317a50715 100644 --- a/gcc/testsuite/gcc.target/gcn/avgpr-mem-double.c +++ b/gcc/testsuite/gcc.target/gcn/avgpr-mem-double.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-additional-options "-march=gfx90a -O1" } */ -/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[068]" } } */ /* { dg-final { scan-assembler {load[^\n]*a[0-9[]} } } */ /* { dg-final { scan-assembler {store[^\n]*a[0-9[]} } } */ diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-mem-int.c b/gcc/testsuite/gcc.target/gcn/avgpr-mem-int.c index 03d81486466..5ea3755e1b8 100644 --- a/gcc/testsuite/gcc.target/gcn/avgpr-mem-int.c +++ b/gcc/testsuite/gcc.target/gcn/avgpr-mem-int.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-additional-options "-march=gfx90a -O1" } */ -/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[068]" } } */ /* { dg-final { scan-assembler {load[^\n]*a[0-9[]} } } */ /* { dg-final { scan-assembler {store[^\n]*a[0-9[]} } } */ diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-mem-long.c b/gcc/testsuite/gcc.target/gcn/avgpr-mem-long.c index dcfb483f3f3..b52fc98da85 100644 --- a/gcc/testsuite/gcc.target/gcn/avgpr-mem-long.c +++ b/gcc/testsuite/gcc.target/gcn/avgpr-mem-long.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-additional-options "-march=gfx90a -O1" } */ -/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[068]" } } */ /* { dg-final { scan-assembler {load[^\n]*a[0-9[]} } } */ /* { dg-final { scan-assembler {store[^\n]*a[0-9[]} } } */ diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-mem-short.c b/gcc/testsuite/gcc.target/gcn/avgpr-mem-short.c index 91cc14ef181..a3e4a8bf9a9 100644 --- a/gcc/testsuite/gcc.target/gcn/avgpr-mem-short.c +++ b/gcc/testsuite/gcc.target/gcn/avgpr-mem-short.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-additional-options "-march=gfx90a -O1" } */ -/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[068]" } } */ /* { dg-final { scan-assembler {load[^\n]*a[0-9[]} } } */ /* { dg-final { scan-assembler {store[^\n]*a[0-9[]} } } */ diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-spill-double.c b/gcc/testsuite/gcc.target/gcn/avgpr-spill-double.c index 3e9996d3d10..53853a4b075 100644 --- a/gcc/testsuite/gcc.target/gcn/avgpr-spill-double.c +++ b/gcc/testsuite/gcc.target/gcn/avgpr-spill-double.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-additional-options "-march=gfx908 -O1" } */ -/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[06]" } } */ /* { dg-final { scan-assembler "accvgpr" } } */ #define TYPE double diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-spill-int.c b/gcc/testsuite/gcc.target/gcn/avgpr-spill-int.c index 0b64c8ec176..650f1587a1b 100644 --- a/gcc/testsuite/gcc.target/gcn/avgpr-spill-int.c +++ b/gcc/testsuite/gcc.target/gcn/avgpr-spill-int.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-additional-options "-march=gfx908 -O1" } */ -/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[06]" } } */ /* { dg-final { scan-assembler "accvgpr" } } */ #ifndef TYPE diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-spill-long.c b/gcc/testsuite/gcc.target/gcn/avgpr-spill-long.c index 516890de14c..51f887c4d59 100644 --- a/gcc/testsuite/gcc.target/gcn/avgpr-spill-long.c +++ b/gcc/testsuite/gcc.target/gcn/avgpr-spill-long.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-additional-options "-march=gfx908 -O1" } */ -/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[06]" } } */ /* { dg-final { scan-assembler "accvgpr" } } */ #define TYPE long diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-spill-short.c b/gcc/testsuite/gcc.target/gcn/avgpr-spill-short.c index 1e556840e0f..983d2017ff5 100644 --- a/gcc/testsuite/gcc.target/gcn/avgpr-spill-short.c +++ b/gcc/testsuite/gcc.target/gcn/avgpr-spill-short.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-additional-options "-march=gfx908 -O1" } */ -/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[06]" } } */ /* { dg-final { scan-assembler "accvgpr" } } */ #define TYPE short -- 2.34.1